mirror of
https://github.com/g4klx/DMRGateway
synced 2025-12-21 05:25:40 +08:00
Move the RF passall processing after all of the other rewrites are done.
This commit is contained in:
@@ -157,7 +157,9 @@ m_xlx2Rewrite(NULL),
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m_dmr1NetRewrites(),
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m_dmr1RFRewrites(),
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m_dmr2NetRewrites(),
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m_dmr2RFRewrites()
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m_dmr2RFRewrites(),
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m_dmr1Passalls(),
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m_dmr2Passalls()
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{
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}
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@@ -175,6 +177,12 @@ CDMRGateway::~CDMRGateway()
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for (std::vector<IRewrite*>::iterator it = m_dmr2RFRewrites.begin(); it != m_dmr2RFRewrites.end(); ++it)
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delete *it;
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for (std::vector<IRewrite*>::iterator it = m_dmr1Passalls.begin(); it != m_dmr1Passalls.end(); ++it)
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delete *it;
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for (std::vector<IRewrite*>::iterator it = m_dmr2Passalls.begin(); it != m_dmr2Passalls.end(); ++it)
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delete *it;
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delete m_rpt1Rewrite;
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delete m_xlx1Rewrite;
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delete m_rpt2Rewrite;
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@@ -565,6 +573,46 @@ int CDMRGateway::run()
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}
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}
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if (!rewritten) {
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if (m_dmrNetwork1 != NULL) {
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for (std::vector<IRewrite*>::iterator it = m_dmr1Passalls.begin(); it != m_dmr1Passalls.end(); ++it) {
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bool ret = (*it)->processRF(data);
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if (ret) {
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rewritten = true;
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break;
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}
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}
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if (rewritten) {
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if (status[slotNo] == DMRGWS_NONE || status[slotNo] == DMRGWS_DMRNETWORK1) {
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m_dmrNetwork1->write(data);
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status[slotNo] = DMRGWS_DMRNETWORK1;
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timer[slotNo]->start();
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}
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}
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}
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}
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if (!rewritten) {
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if (m_dmrNetwork2 != NULL) {
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for (std::vector<IRewrite*>::iterator it = m_dmr2Passalls.begin(); it != m_dmr2Passalls.end(); ++it) {
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bool ret = (*it)->processRF(data);
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if (ret) {
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rewritten = true;
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break;
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}
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}
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if (rewritten) {
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if (status[slotNo] == DMRGWS_NONE || status[slotNo] == DMRGWS_DMRNETWORK2) {
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m_dmrNetwork2->write(data);
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status[slotNo] = DMRGWS_DMRNETWORK2;
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timer[slotNo]->start();
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}
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}
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}
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}
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if (!rewritten && ruleTrace)
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LogDebug("Rule Trace,\tnot matched so rejected");
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}
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@@ -763,8 +811,6 @@ int CDMRGateway::run()
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CThread::sleep(10U);
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}
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// LogMessage("DMRGateway-%s is exiting on receipt of SIGHUP1", VERSION);
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delete voice1;
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delete voice2;
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@@ -913,7 +959,7 @@ bool CDMRGateway::createDMRNetwork1(bool trace)
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CPassAllTG* rfPassAllTG = new CPassAllTG("DMR-1", *it, trace);
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CPassAllTG* netPassAllTG = new CPassAllTG("DMR-1", *it, trace);
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m_dmr1RFRewrites.push_back(rfPassAllTG);
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m_dmr1Passalls.push_back(rfPassAllTG);
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m_dmr1NetRewrites.push_back(netPassAllTG);
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}
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@@ -924,7 +970,7 @@ bool CDMRGateway::createDMRNetwork1(bool trace)
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CPassAllPC* rfPassAllPC = new CPassAllPC("DMR-1", *it, trace);
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CPassAllPC* netPassAllPC = new CPassAllPC("DMR-1", *it, trace);
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m_dmr1RFRewrites.push_back(rfPassAllPC);
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m_dmr1Passalls.push_back(rfPassAllPC);
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m_dmr1NetRewrites.push_back(netPassAllPC);
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}
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@@ -1021,7 +1067,7 @@ bool CDMRGateway::createDMRNetwork2(bool trace)
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CPassAllTG* rfPassAllTG = new CPassAllTG("DMR-2", *it, trace);
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CPassAllTG* netPassAllTG = new CPassAllTG("DMR-2", *it, trace);
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m_dmr2RFRewrites.push_back(rfPassAllTG);
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m_dmr2Passalls.push_back(rfPassAllTG);
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m_dmr2NetRewrites.push_back(netPassAllTG);
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}
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@@ -1032,7 +1078,7 @@ bool CDMRGateway::createDMRNetwork2(bool trace)
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CPassAllPC* rfPassAllPC = new CPassAllPC("DMR-2", *it, trace);
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CPassAllPC* netPassAllPC = new CPassAllPC("DMR-2", *it, trace);
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m_dmr2RFRewrites.push_back(rfPassAllPC);
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m_dmr2Passalls.push_back(rfPassAllPC);
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m_dmr2NetRewrites.push_back(netPassAllPC);
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}
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@@ -65,6 +65,8 @@ private:
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std::vector<IRewrite*> m_dmr1RFRewrites;
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std::vector<IRewrite*> m_dmr2NetRewrites;
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std::vector<IRewrite*> m_dmr2RFRewrites;
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std::vector<IRewrite*> m_dmr1Passalls;
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std::vector<IRewrite*> m_dmr2Passalls;
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bool createMMDVM();
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bool createDMRNetwork1(bool trace);
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