From f90dbb587413a4cf56bec4867537537a0aff4fc9 Mon Sep 17 00:00:00 2001 From: Jonathan Naylor Date: Tue, 30 May 2017 21:52:44 +0100 Subject: [PATCH 01/20] Add informative messages at startup. --- DMRGateway.cpp | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-) diff --git a/DMRGateway.cpp b/DMRGateway.cpp index 2d68556..c4f6a76 100644 --- a/DMRGateway.cpp +++ b/DMRGateway.cpp @@ -363,6 +363,7 @@ int CDMRGateway::run() if (connected && !m_xlx1Connected) { if (m_xlx1Startup != 4000U) { writeXLXLink(m_xlx1Id, m_xlx1Startup, m_xlxNetwork1); + LogMessage("XLX-1, Linking to reflector %u at startup", m_xlx1Startup); if (voice1 != NULL) voice1->linkedTo(m_xlx1Startup); } @@ -370,8 +371,11 @@ int CDMRGateway::run() m_xlx1Reflector = m_xlx1Startup; m_xlx1Connected = true; } else if (!connected && m_xlx1Connected) { - if (m_xlx1Reflector != 4000U && voice1 != NULL) - voice1->unlinked(); + if (m_xlx1Reflector != 4000U) { + LogMessage("XLX-1, Unlinking due to loss of connection"); + if (voice1 != NULL) + voice1->unlinked(); + } m_xlx1Reflector = 4000U; m_xlx1Connected = false; @@ -383,6 +387,7 @@ int CDMRGateway::run() if (connected && !m_xlx2Connected) { if (m_xlx2Startup != 4000U) { writeXLXLink(m_xlx2Id, m_xlx2Startup, m_xlxNetwork2); + LogMessage("XLX-2, Linking to reflector %u at startup", m_xlx2Startup); if (voice2 != NULL) voice2->linkedTo(m_xlx2Startup); } @@ -390,8 +395,11 @@ int CDMRGateway::run() m_xlx2Reflector = m_xlx2Startup; m_xlx2Connected = true; } else if (!connected && m_xlx2Connected) { - if (m_xlx2Reflector != 4000U && voice2 != NULL) - voice2->unlinked(); + if (m_xlx2Reflector != 4000U) { + LogMessage("XLX-2, Unlinking due to loss of connection"); + if (voice2 != NULL) + voice2->unlinked(); + } m_xlx2Reflector = 4000U; m_xlx2Connected = false; From 9914c43e1a6e6e82a1f80ae127aba4afc2617559 Mon Sep 17 00:00:00 2001 From: g0wfv Date: Thu, 1 Jun 2017 16:40:14 +0100 Subject: [PATCH 02/20] Add status request (while connected only I think) to XLX - PC to 5000 (plus base!) --- DMRGateway.cpp | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/DMRGateway.cpp b/DMRGateway.cpp index 2d68556..43d5003 100644 --- a/DMRGateway.cpp +++ b/DMRGateway.cpp @@ -424,6 +424,9 @@ int CDMRGateway::run() if (dstId != m_xlx1Reflector) { if (dstId == 4000U) { LogMessage("XLX-1, Unlinking"); + } elseif (dstId == 5000U) { + // Status XLX-1 here + voice1->linkedTo(m_xlx1Reflector); } else { if (m_xlx1Reflector != 4000U) writeXLXLink(srcId, 4000U, m_xlxNetwork1); @@ -458,6 +461,9 @@ int CDMRGateway::run() if (dstId != m_xlx2Reflector) { if (dstId == 4000U) { LogMessage("XLX-2, Unlinking"); + } elseif (dstId == 5000U) { + // Status XLX-2 here + voice2->linkedTo(m_xlx1Reflector); } else { if (m_xlx2Reflector != 4000U) writeXLXLink(srcId, 4000U, m_xlxNetwork2); From d9b0410fa00bad028f502d1ecd382c75ba02c182 Mon Sep 17 00:00:00 2001 From: Tony Corbett G0WFV Date: Thu, 1 Jun 2017 17:34:51 +0100 Subject: [PATCH 03/20] Add status when connected or disconnected via PC to 5000 +/- base! --- DMRGateway.cpp | 36 ++++++++++++++++++++++-------------- 1 file changed, 22 insertions(+), 14 deletions(-) diff --git a/DMRGateway.cpp b/DMRGateway.cpp index 444cda6..3452500 100644 --- a/DMRGateway.cpp +++ b/DMRGateway.cpp @@ -425,16 +425,18 @@ int CDMRGateway::run() m_xlxNetwork2->write(data); status[slotNo] = DMRGWS_XLXREFLECTOR2; timer[slotNo]->start(); - } else if (flco == FLCO_USER_USER && slotNo == m_xlx1Slot && dstId >= m_xlx1Base && dstId <= (m_xlx1Base + 26U)) { + } else if ((dstId <= (m_xlx1Base + 26U) || dstId == (m_xlx1Base + 1000U)) && flco == FLCO_USER_USER && slotNo == m_xlx1Slot && dstId >= m_xlx1Base) { // dstId += 4000U; dstId -= m_xlx1Base; if (dstId != m_xlx1Reflector) { if (dstId == 4000U) { LogMessage("XLX-1, Unlinking"); - } elseif (dstId == 5000U) { - // Status XLX-1 here - voice1->linkedTo(m_xlx1Reflector); + } else if (dstId == 5000U) { + if (m_xlx1Reflector != 4000) + voice1->linkedTo(m_xlx1Reflector); + else + voice1->unlinked(); } else { if (m_xlx1Reflector != 4000U) writeXLXLink(srcId, 4000U, m_xlxNetwork1); @@ -442,9 +444,11 @@ int CDMRGateway::run() LogMessage("XLX-1, Linking to reflector %u", dstId); } - writeXLXLink(srcId, dstId, m_xlxNetwork1); - m_xlx1Reflector = dstId; - changed = true; + if (dstId != 5000U ) { + writeXLXLink(srcId, dstId, m_xlxNetwork1); + m_xlx1Reflector = dstId; + changed = true; + } } status[slotNo] = DMRGWS_XLXREFLECTOR1; @@ -462,16 +466,18 @@ int CDMRGateway::run() } } } - } else if (flco == FLCO_USER_USER && slotNo == m_xlx2Slot && dstId >= m_xlx2Base && dstId <= (m_xlx2Base + 26U)) { + } else if ((dstId <= (m_xlx2Base + 26U) || dstId == (m_xlx2Base + 1000U)) && flco == FLCO_USER_USER && slotNo == m_xlx2Slot && dstId >= m_xlx2Base) { // dstId += 4000U; dstId -= m_xlx2Base; if (dstId != m_xlx2Reflector) { if (dstId == 4000U) { LogMessage("XLX-2, Unlinking"); - } elseif (dstId == 5000U) { - // Status XLX-2 here - voice2->linkedTo(m_xlx1Reflector); + } else if (dstId == 5000U) { + if (m_xlx2Reflector != 4000) + voice2->linkedTo(m_xlx2Reflector); + else + voice2->unlinked(); } else { if (m_xlx2Reflector != 4000U) writeXLXLink(srcId, 4000U, m_xlxNetwork2); @@ -479,9 +485,11 @@ int CDMRGateway::run() LogMessage("XLX-2, Linking to reflector %u", dstId); } - writeXLXLink(srcId, dstId, m_xlxNetwork2); - m_xlx2Reflector = dstId; - changed = true; + if (dstId != 5000U ) { + writeXLXLink(srcId, dstId, m_xlxNetwork2); + m_xlx2Reflector = dstId; + changed = true; + } } status[slotNo] = DMRGWS_XLXREFLECTOR2; From c8fbef105145345c1d2194149d35ece22a4dbd44 Mon Sep 17 00:00:00 2001 From: Tony Corbett G0WFV Date: Thu, 1 Jun 2017 17:41:16 +0100 Subject: [PATCH 04/20] Cleanup --- DMRGateway.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/DMRGateway.cpp b/DMRGateway.cpp index 3452500..a76da9d 100644 --- a/DMRGateway.cpp +++ b/DMRGateway.cpp @@ -425,7 +425,7 @@ int CDMRGateway::run() m_xlxNetwork2->write(data); status[slotNo] = DMRGWS_XLXREFLECTOR2; timer[slotNo]->start(); - } else if ((dstId <= (m_xlx1Base + 26U) || dstId == (m_xlx1Base + 1000U)) && flco == FLCO_USER_USER && slotNo == m_xlx1Slot && dstId >= m_xlx1Base) { // + } else if ((dstId <= (m_xlx1Base + 26U) || dstId == (m_xlx1Base + 1000U)) && flco == FLCO_USER_USER && slotNo == m_xlx1Slot && dstId >= m_xlx1Base) { dstId += 4000U; dstId -= m_xlx1Base; @@ -466,7 +466,7 @@ int CDMRGateway::run() } } } - } else if ((dstId <= (m_xlx2Base + 26U) || dstId == (m_xlx2Base + 1000U)) && flco == FLCO_USER_USER && slotNo == m_xlx2Slot && dstId >= m_xlx2Base) { // + } else if ((dstId <= (m_xlx2Base + 26U) || dstId == (m_xlx2Base + 1000U)) && flco == FLCO_USER_USER && slotNo == m_xlx2Slot && dstId >= m_xlx2Base) { dstId += 4000U; dstId -= m_xlx2Base; From b92b119e8dfa0a2ba271e0480dfac1f28d8e96c2 Mon Sep 17 00:00:00 2001 From: g0wfv Date: Thu, 1 Jun 2017 18:18:30 +0100 Subject: [PATCH 05/20] Satisfying my CDO --- DMRGateway.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/DMRGateway.cpp b/DMRGateway.cpp index a76da9d..138a49c 100644 --- a/DMRGateway.cpp +++ b/DMRGateway.cpp @@ -433,7 +433,7 @@ int CDMRGateway::run() if (dstId == 4000U) { LogMessage("XLX-1, Unlinking"); } else if (dstId == 5000U) { - if (m_xlx1Reflector != 4000) + if (m_xlx1Reflector != 4000U) voice1->linkedTo(m_xlx1Reflector); else voice1->unlinked(); @@ -474,7 +474,7 @@ int CDMRGateway::run() if (dstId == 4000U) { LogMessage("XLX-2, Unlinking"); } else if (dstId == 5000U) { - if (m_xlx2Reflector != 4000) + if (m_xlx2Reflector != 4000U) voice2->linkedTo(m_xlx2Reflector); else voice2->unlinked(); From fc70b6813ce5859f1e0ae3a323277b5e3cbf3469 Mon Sep 17 00:00:00 2001 From: Tony Corbett G0WFV Date: Fri, 2 Jun 2017 11:42:54 +0100 Subject: [PATCH 06/20] Stop gateway bombing out when MMDVMHost stops after the gateway has restarted --- DMRGateway.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/DMRGateway.cpp b/DMRGateway.cpp index 138a49c..017aa36 100644 --- a/DMRGateway.cpp +++ b/DMRGateway.cpp @@ -268,7 +268,7 @@ int CDMRGateway::run() while (!m_killed) { unsigned char config[400U]; unsigned int len = m_repeater->getConfig(config); - if (len > 0U) + if (len > 0U && m_repeater->getId() > 1000U) break; m_repeater->clock(10U); From efbf42ff83dacd62a733a43b8de9963d7c653515 Mon Sep 17 00:00:00 2001 From: Jonathan Naylor Date: Fri, 2 Jun 2017 16:29:01 +0100 Subject: [PATCH 07/20] Allow for passing of beacon requests from the networks to the repeater. --- DMRGateway.cpp | 8 ++++++++ MMDVMNetwork.cpp | 9 +++++++++ MMDVMNetwork.h | 2 ++ RepeaterProtocol.h | 2 ++ 4 files changed, 21 insertions(+) diff --git a/DMRGateway.cpp b/DMRGateway.cpp index 017aa36..2c148ab 100644 --- a/DMRGateway.cpp +++ b/DMRGateway.cpp @@ -615,6 +615,10 @@ int CDMRGateway::run() } } } + + ret = m_dmrNetwork1->wantsBeacon(); + if (ret) + m_repeater->writeBeacon(); } if (m_dmrNetwork2 != NULL) { @@ -639,6 +643,10 @@ int CDMRGateway::run() } } } + + ret = m_dmrNetwork2->wantsBeacon(); + if (ret) + m_repeater->writeBeacon(); } unsigned char buffer[50U]; diff --git a/MMDVMNetwork.cpp b/MMDVMNetwork.cpp index 3179d51..aadc537 100644 --- a/MMDVMNetwork.cpp +++ b/MMDVMNetwork.cpp @@ -244,6 +244,15 @@ bool CMMDVMNetwork::readTalkerAlias(unsigned char* data, unsigned int& length) return true; } +bool CMMDVMNetwork::writeBeacon() +{ + unsigned char buffer[20U]; + ::memcpy(buffer + 0U, "RPTSBKN", 7U); + ::memcpy(buffer + 7U, m_netId, 4U); + + return m_socket.write(buffer, 11U, m_rptAddress, m_rptPort); +} + void CMMDVMNetwork::close() { LogMessage("DMR, Closing MMDVM Network"); diff --git a/MMDVMNetwork.h b/MMDVMNetwork.h index 58d7990..3240705 100644 --- a/MMDVMNetwork.h +++ b/MMDVMNetwork.h @@ -50,6 +50,8 @@ public: virtual bool readTalkerAlias(unsigned char* data, unsigned int& length); + virtual bool writeBeacon(); + virtual void clock(unsigned int ms); virtual void close(); diff --git a/RepeaterProtocol.h b/RepeaterProtocol.h index d15019c..6f602f3 100644 --- a/RepeaterProtocol.h +++ b/RepeaterProtocol.h @@ -45,6 +45,8 @@ public: virtual void clock(unsigned int ms) = 0; + virtual bool writeBeacon() = 0; + virtual void close() = 0; private: From 2e257da997344bfbc8261f8324c954415072b756 Mon Sep 17 00:00:00 2001 From: Jonathan Naylor Date: Sun, 4 Jun 2017 15:17:43 +0100 Subject: [PATCH 08/20] Add basic rule tracing. --- Conf.cpp | 8 +++++ Conf.h | 2 ++ DMRGateway.cpp | 85 ++++++++++++++++++++++++++++++++++--------------- DMRGateway.h | 1 + DMRGateway.ini | 1 + PassAllPC.cpp | 20 +++++++++--- PassAllPC.h | 3 +- PassAllTG.cpp | 20 +++++++++--- PassAllTG.h | 3 +- RewritePC.cpp | 18 +++++++++-- RewritePC.h | 3 +- RewriteSrc.cpp | 17 ++++++++-- RewriteSrc.h | 3 +- RewriteTG.cpp | 22 ++++++++++--- RewriteTG.h | 3 +- RewriteType.cpp | 21 +++++++++--- RewriteType.h | 3 +- 17 files changed, 177 insertions(+), 56 deletions(-) diff --git a/Conf.cpp b/Conf.cpp index 0f1f10b..d6b86bc 100644 --- a/Conf.cpp +++ b/Conf.cpp @@ -45,6 +45,7 @@ m_rptPort(62032U), m_localAddress("127.0.0.1"), m_localPort(62031U), m_timeout(10U), +m_ruleTrace(false), m_debug(false), m_voiceEnabled(true), m_voiceLanguage("en_GB"), @@ -169,6 +170,8 @@ bool CConf::read() m_localAddress = value; else if (::strcmp(key, "LocalPort") == 0) m_localPort = (unsigned int)::atoi(value); + else if (::strcmp(key, "RuleTrace") == 0) + m_ruleTrace = ::atoi(value) == 1; else if (::strcmp(key, "Debug") == 0) m_debug = ::atoi(value) == 1; } else if (section == SECTION_LOG) { @@ -439,6 +442,11 @@ unsigned int CConf::getTimeout() const return m_timeout; } +bool CConf::getRuleTrace() const +{ + return m_ruleTrace; +} + bool CConf::getDebug() const { return m_debug; diff --git a/Conf.h b/Conf.h index 5e5288d..9f17c37 100644 --- a/Conf.h +++ b/Conf.h @@ -68,6 +68,7 @@ public: unsigned int getRptPort() const; std::string getLocalAddress() const; unsigned int getLocalPort() const; + bool getRuleTrace() const; bool getDebug() const; // The Log section @@ -149,6 +150,7 @@ private: std::string m_localAddress; unsigned int m_localPort; unsigned int m_timeout; + bool m_ruleTrace; bool m_debug; bool m_voiceEnabled; diff --git a/DMRGateway.cpp b/DMRGateway.cpp index 2c148ab..ae940a6 100644 --- a/DMRGateway.cpp +++ b/DMRGateway.cpp @@ -127,6 +127,7 @@ int main(int argc, char** argv) CDMRGateway::CDMRGateway(const std::string& confFile) : m_conf(confFile), +m_ruleTrace(false), m_repeater(NULL), m_dmrNetwork1(NULL), m_dmrNetwork2(NULL), @@ -342,6 +343,9 @@ int CDMRGateway::run() } } + m_ruleTrace = m_conf.getRuleTrace(); + LogInfo("Rule trace: %s", m_ruleTrace ? "yes" : "no"); + CTimer* timer[3U]; timer[1U] = new CTimer(1000U, timeout); timer[2U] = new CTimer(1000U, timeout); @@ -508,6 +512,14 @@ int CDMRGateway::run() } } } else { + unsigned int slotNo = data.getSlotNo(); + unsigned int srcId = data.getSrcId(); + unsigned int dstId = data.getDstId(); + FLCO flco = data.getFLCO(); + + if (m_ruleTrace) + LogDebug("Rule Trace, RF transmission: S%u %u -> %s%u", slotNo, srcId, flco == FLCO_GROUP ? "TG" : "", dstId); + bool rewritten = false; if (m_dmrNetwork1 != NULL) { @@ -521,7 +533,6 @@ int CDMRGateway::run() } if (rewritten) { - unsigned int slotNo = data.getSlotNo(); if (status[slotNo] == DMRGWS_NONE || status[slotNo] == DMRGWS_DMRNETWORK1) { m_dmrNetwork1->write(data); status[slotNo] = DMRGWS_DMRNETWORK1; @@ -542,7 +553,6 @@ int CDMRGateway::run() } if (rewritten) { - unsigned int slotNo = data.getSlotNo(); if (status[slotNo] == DMRGWS_NONE || status[slotNo] == DMRGWS_DMRNETWORK2) { m_dmrNetwork2->write(data); status[slotNo] = DMRGWS_DMRNETWORK2; @@ -551,6 +561,9 @@ int CDMRGateway::run() } } } + + if (!rewritten && m_ruleTrace) + LogDebug("Rule Trace,\tnot matched so rejected"); } } @@ -596,6 +609,14 @@ int CDMRGateway::run() if (m_dmrNetwork1 != NULL) { ret = m_dmrNetwork1->read(data); if (ret) { + unsigned int slotNo = data.getSlotNo(); + unsigned int srcId = data.getSrcId(); + unsigned int dstId = data.getDstId(); + FLCO flco = data.getFLCO(); + + if (m_ruleTrace) + LogDebug("Rule Trace, network 1 transmission: S%u %u -> %s%u", slotNo, srcId, flco == FLCO_GROUP ? "TG" : "", dstId); + // Rewrite the slot and/or TG or neither bool rewritten = false; for (std::vector::iterator it = m_dmr1NetRewrites.begin(); it != m_dmr1NetRewrites.end(); ++it) { @@ -607,13 +628,15 @@ int CDMRGateway::run() } if (rewritten) { - unsigned int slotNo = data.getSlotNo(); if (status[slotNo] == DMRGWS_NONE || status[slotNo] == DMRGWS_DMRNETWORK1) { m_repeater->write(data); status[slotNo] = DMRGWS_DMRNETWORK1; timer[slotNo]->start(); } } + + if (!rewritten && m_ruleTrace) + LogDebug("Rule Trace,\tnot matched so rejected"); } ret = m_dmrNetwork1->wantsBeacon(); @@ -624,6 +647,14 @@ int CDMRGateway::run() if (m_dmrNetwork2 != NULL) { ret = m_dmrNetwork2->read(data); if (ret) { + unsigned int slotNo = data.getSlotNo(); + unsigned int srcId = data.getSrcId(); + unsigned int dstId = data.getDstId(); + FLCO flco = data.getFLCO(); + + if (m_ruleTrace) + LogDebug("Rule Trace, network 2 transmission: S%u %u -> %s%u", slotNo, srcId, flco == FLCO_GROUP ? "TG" : "", dstId); + // Rewrite the slot and/or TG or neither bool rewritten = false; for (std::vector::iterator it = m_dmr2NetRewrites.begin(); it != m_dmr2NetRewrites.end(); ++it) { @@ -635,13 +666,15 @@ int CDMRGateway::run() } if (rewritten) { - unsigned int slotNo = data.getSlotNo(); if (status[slotNo] == DMRGWS_NONE || status[slotNo] == DMRGWS_DMRNETWORK2) { m_repeater->write(data); status[slotNo] = DMRGWS_DMRNETWORK2; timer[slotNo]->start(); } } + + if (!rewritten && m_ruleTrace) + LogDebug("Rule Trace,\tnot matched so rejected"); } ret = m_dmrNetwork2->wantsBeacon(); @@ -836,8 +869,8 @@ bool CDMRGateway::createDMRNetwork1() LogInfo(" Rewrite RF: %u:TG%u-TG%u -> %u:TG%u-TG%u", (*it).m_fromSlot, (*it).m_fromTG, (*it).m_fromTG + (*it).m_range - 1U, (*it).m_toSlot, (*it).m_toTG, (*it).m_toTG + (*it).m_range - 1U); LogInfo(" Rewrite Net: %u:TG%u-TG%u -> %u:TG%u-TG%u", (*it).m_toSlot, (*it).m_toTG, (*it).m_toTG + (*it).m_range - 1U, (*it).m_fromSlot, (*it).m_fromTG, (*it).m_fromTG + (*it).m_range - 1U); - CRewriteTG* rfRewrite = new CRewriteTG("DMR-1", (*it).m_fromSlot, (*it).m_fromTG, (*it).m_toSlot, (*it).m_toTG, (*it).m_range); - CRewriteTG* netRewrite = new CRewriteTG("DMR-1", (*it).m_toSlot, (*it).m_toTG, (*it).m_fromSlot, (*it).m_fromTG, (*it).m_range); + CRewriteTG* rfRewrite = new CRewriteTG("DMR-1", (*it).m_fromSlot, (*it).m_fromTG, (*it).m_toSlot, (*it).m_toTG, (*it).m_range, m_ruleTrace); + CRewriteTG* netRewrite = new CRewriteTG("DMR-1", (*it).m_toSlot, (*it).m_toTG, (*it).m_fromSlot, (*it).m_fromTG, (*it).m_range, m_ruleTrace); m_dmr1RFRewrites.push_back(rfRewrite); m_dmr1NetRewrites.push_back(netRewrite); @@ -847,7 +880,7 @@ bool CDMRGateway::createDMRNetwork1() for (std::vector::const_iterator it = pcRewrites.begin(); it != pcRewrites.end(); ++it) { LogInfo(" Rewrite RF: %u:%u-%u -> %u:%u-%u", (*it).m_fromSlot, (*it).m_fromId, (*it).m_fromId + (*it).m_range - 1U, (*it).m_toSlot, (*it).m_toId, (*it).m_toId + (*it).m_range - 1U); - CRewritePC* rewrite = new CRewritePC("DMR-1", (*it).m_fromSlot, (*it).m_fromId, (*it).m_toSlot, (*it).m_toId, (*it).m_range); + CRewritePC* rewrite = new CRewritePC("DMR-1", (*it).m_fromSlot, (*it).m_fromId, (*it).m_toSlot, (*it).m_toId, (*it).m_range, m_ruleTrace); m_dmr1RFRewrites.push_back(rewrite); } @@ -856,7 +889,7 @@ bool CDMRGateway::createDMRNetwork1() for (std::vector::const_iterator it = typeRewrites.begin(); it != typeRewrites.end(); ++it) { LogInfo(" Rewrite RF: %u:TG%u -> %u:%u", (*it).m_fromSlot, (*it).m_fromTG, (*it).m_toSlot, (*it).m_toId); - CRewriteType* rewrite = new CRewriteType("DMR-1", (*it).m_fromSlot, (*it).m_fromTG, (*it).m_toSlot, (*it).m_toId); + CRewriteType* rewrite = new CRewriteType("DMR-1", (*it).m_fromSlot, (*it).m_fromTG, (*it).m_toSlot, (*it).m_toId, m_ruleTrace); m_dmr1RFRewrites.push_back(rewrite); } @@ -865,7 +898,7 @@ bool CDMRGateway::createDMRNetwork1() for (std::vector::const_iterator it = srcRewrites.begin(); it != srcRewrites.end(); ++it) { LogInfo(" Rewrite Net: %u:%u-%u -> %u:TG%u", (*it).m_fromSlot, (*it).m_fromId, (*it).m_fromId + (*it).m_range - 1U, (*it).m_toSlot, (*it).m_toTG); - CRewriteSrc* rewrite = new CRewriteSrc("DMR-1", (*it).m_fromSlot, (*it).m_fromId, (*it).m_toSlot, (*it).m_toTG, (*it).m_range); + CRewriteSrc* rewrite = new CRewriteSrc("DMR-1", (*it).m_fromSlot, (*it).m_fromId, (*it).m_toSlot, (*it).m_toTG, (*it).m_range, m_ruleTrace); m_dmr1NetRewrites.push_back(rewrite); } @@ -874,8 +907,8 @@ bool CDMRGateway::createDMRNetwork1() for (std::vector::const_iterator it = tgPassAll.begin(); it != tgPassAll.end(); ++it) { LogInfo(" Pass All TG: %u", *it); - CPassAllTG* rfPassAllTG = new CPassAllTG("DMR-1", *it); - CPassAllTG* netPassAllTG = new CPassAllTG("DMR-1", *it); + CPassAllTG* rfPassAllTG = new CPassAllTG("DMR-1", *it, m_ruleTrace); + CPassAllTG* netPassAllTG = new CPassAllTG("DMR-1", *it, m_ruleTrace); m_dmr1RFRewrites.push_back(rfPassAllTG); m_dmr1NetRewrites.push_back(netPassAllTG); @@ -885,8 +918,8 @@ bool CDMRGateway::createDMRNetwork1() for (std::vector::const_iterator it = pcPassAll.begin(); it != pcPassAll.end(); ++it) { LogInfo(" Pass All PC: %u", *it); - CPassAllPC* rfPassAllPC = new CPassAllPC("DMR-1", *it); - CPassAllPC* netPassAllPC = new CPassAllPC("DMR-1", *it); + CPassAllPC* rfPassAllPC = new CPassAllPC("DMR-1", *it, m_ruleTrace); + CPassAllPC* netPassAllPC = new CPassAllPC("DMR-1", *it, m_ruleTrace); m_dmr1RFRewrites.push_back(rfPassAllPC); m_dmr1NetRewrites.push_back(netPassAllPC); @@ -944,8 +977,8 @@ bool CDMRGateway::createDMRNetwork2() LogInfo(" Rewrite RF: %u:TG%u-TG%u -> %u:TG%u-TG%u", (*it).m_fromSlot, (*it).m_fromTG, (*it).m_fromTG + (*it).m_range - 1U, (*it).m_toSlot, (*it).m_toTG, (*it).m_toTG + (*it).m_range - 1U); LogInfo(" Rewrite Net: %u:TG%u-TG%u -> %u:TG%u-TG%u", (*it).m_toSlot, (*it).m_toTG, (*it).m_toTG + (*it).m_range - 1U, (*it).m_fromSlot, (*it).m_fromTG, (*it).m_fromTG + (*it).m_range - 1U); - CRewriteTG* rfRewrite = new CRewriteTG("DMR-2", (*it).m_fromSlot, (*it).m_fromTG, (*it).m_toSlot, (*it).m_toTG, (*it).m_range); - CRewriteTG* netRewrite = new CRewriteTG("DMR-2", (*it).m_toSlot, (*it).m_toTG, (*it).m_fromSlot, (*it).m_fromTG, (*it).m_range); + CRewriteTG* rfRewrite = new CRewriteTG("DMR-2", (*it).m_fromSlot, (*it).m_fromTG, (*it).m_toSlot, (*it).m_toTG, (*it).m_range, m_ruleTrace); + CRewriteTG* netRewrite = new CRewriteTG("DMR-2", (*it).m_toSlot, (*it).m_toTG, (*it).m_fromSlot, (*it).m_fromTG, (*it).m_range, m_ruleTrace); m_dmr2RFRewrites.push_back(rfRewrite); m_dmr2NetRewrites.push_back(netRewrite); @@ -955,7 +988,7 @@ bool CDMRGateway::createDMRNetwork2() for (std::vector::const_iterator it = pcRewrites.begin(); it != pcRewrites.end(); ++it) { LogInfo(" Rewrite RF: %u:%u-%u -> %u:%u-%u", (*it).m_fromSlot, (*it).m_fromId, (*it).m_fromId + (*it).m_range - 1U, (*it).m_toSlot, (*it).m_toId, (*it).m_toId + (*it).m_range - 1U); - CRewritePC* rewrite = new CRewritePC("DMR-2", (*it).m_fromSlot, (*it).m_fromId, (*it).m_toSlot, (*it).m_toId, (*it).m_range); + CRewritePC* rewrite = new CRewritePC("DMR-2", (*it).m_fromSlot, (*it).m_fromId, (*it).m_toSlot, (*it).m_toId, (*it).m_range, m_ruleTrace); m_dmr2RFRewrites.push_back(rewrite); } @@ -964,7 +997,7 @@ bool CDMRGateway::createDMRNetwork2() for (std::vector::const_iterator it = typeRewrites.begin(); it != typeRewrites.end(); ++it) { LogInfo(" Rewrite RF: %u:TG%u -> %u:%u", (*it).m_fromSlot, (*it).m_fromTG, (*it).m_toSlot, (*it).m_toId); - CRewriteType* rewrite = new CRewriteType("DMR-2", (*it).m_fromSlot, (*it).m_fromTG, (*it).m_toSlot, (*it).m_toId); + CRewriteType* rewrite = new CRewriteType("DMR-2", (*it).m_fromSlot, (*it).m_fromTG, (*it).m_toSlot, (*it).m_toId, m_ruleTrace); m_dmr2RFRewrites.push_back(rewrite); } @@ -973,7 +1006,7 @@ bool CDMRGateway::createDMRNetwork2() for (std::vector::const_iterator it = srcRewrites.begin(); it != srcRewrites.end(); ++it) { LogInfo(" Rewrite Net: %u:%u-%u -> %u:TG%u", (*it).m_fromSlot, (*it).m_fromId, (*it).m_fromId + (*it).m_range - 1U, (*it).m_toSlot, (*it).m_toTG); - CRewriteSrc* rewrite = new CRewriteSrc("DMR-2", (*it).m_fromSlot, (*it).m_fromId, (*it).m_toSlot, (*it).m_toTG, (*it).m_range); + CRewriteSrc* rewrite = new CRewriteSrc("DMR-2", (*it).m_fromSlot, (*it).m_fromId, (*it).m_toSlot, (*it).m_toTG, (*it).m_range, m_ruleTrace); m_dmr2NetRewrites.push_back(rewrite); } @@ -982,8 +1015,8 @@ bool CDMRGateway::createDMRNetwork2() for (std::vector::const_iterator it = tgPassAll.begin(); it != tgPassAll.end(); ++it) { LogInfo(" Pass All TG: %u", *it); - CPassAllTG* rfPassAllTG = new CPassAllTG("DMR-2", *it); - CPassAllTG* netPassAllTG = new CPassAllTG("DMR-2", *it); + CPassAllTG* rfPassAllTG = new CPassAllTG("DMR-2", *it, m_ruleTrace); + CPassAllTG* netPassAllTG = new CPassAllTG("DMR-2", *it, m_ruleTrace); m_dmr2RFRewrites.push_back(rfPassAllTG); m_dmr2NetRewrites.push_back(netPassAllTG); @@ -993,8 +1026,8 @@ bool CDMRGateway::createDMRNetwork2() for (std::vector::const_iterator it = pcPassAll.begin(); it != pcPassAll.end(); ++it) { LogInfo(" Pass All PC: %u", *it); - CPassAllPC* rfPassAllPC = new CPassAllPC("DMR-2", *it); - CPassAllPC* netPassAllPC = new CPassAllPC("DMR-2", *it); + CPassAllPC* rfPassAllPC = new CPassAllPC("DMR-2", *it, m_ruleTrace); + CPassAllPC* netPassAllPC = new CPassAllPC("DMR-2", *it, m_ruleTrace); m_dmr2RFRewrites.push_back(rfPassAllPC); m_dmr2NetRewrites.push_back(netPassAllPC); @@ -1055,8 +1088,8 @@ bool CDMRGateway::createXLXNetwork1() if (m_xlx1Startup != 4000U) LogInfo(" Startup: %u", m_xlx1Startup); - m_rpt1Rewrite = new CRewriteTG("XLX-1", XLX_SLOT, XLX_TG, m_xlx1Slot, m_xlx1TG, 1U); - m_xlx1Rewrite = new CRewriteTG("XLX-1", m_xlx1Slot, m_xlx1TG, XLX_SLOT, XLX_TG, 1U); + m_rpt1Rewrite = new CRewriteTG("XLX-1", XLX_SLOT, XLX_TG, m_xlx1Slot, m_xlx1TG, 1U, false); + m_xlx1Rewrite = new CRewriteTG("XLX-1", m_xlx1Slot, m_xlx1TG, XLX_SLOT, XLX_TG, 1U, false); return true; } @@ -1113,8 +1146,8 @@ bool CDMRGateway::createXLXNetwork2() if (m_xlx2Startup != 4000U) LogInfo(" Startup: %u", m_xlx2Startup); - m_rpt2Rewrite = new CRewriteTG("XLX-2", XLX_SLOT, XLX_TG, m_xlx2Slot, m_xlx2TG, 1U); - m_xlx2Rewrite = new CRewriteTG("XLX-2", m_xlx2Slot, m_xlx2TG, XLX_SLOT, XLX_TG, 1U); + m_rpt2Rewrite = new CRewriteTG("XLX-2", XLX_SLOT, XLX_TG, m_xlx2Slot, m_xlx2TG, 1U, false); + m_xlx2Rewrite = new CRewriteTG("XLX-2", m_xlx2Slot, m_xlx2TG, XLX_SLOT, XLX_TG, 1U, false); return true; } diff --git a/DMRGateway.h b/DMRGateway.h index 3f3afd9..bae8be1 100644 --- a/DMRGateway.h +++ b/DMRGateway.h @@ -38,6 +38,7 @@ public: private: CConf m_conf; + bool m_ruleTrace; IRepeaterProtocol* m_repeater; CDMRNetwork* m_dmrNetwork1; CDMRNetwork* m_dmrNetwork2; diff --git a/DMRGateway.ini b/DMRGateway.ini index 596589a..ed824ea 100644 --- a/DMRGateway.ini +++ b/DMRGateway.ini @@ -4,6 +4,7 @@ RptAddress=127.0.0.1 RptPort=62032 LocalAddress=127.0.0.1 LocalPort=62031 +RuleTrace=0 Daemon=0 Debug=0 diff --git a/PassAllPC.cpp b/PassAllPC.cpp index 0094093..8852efb 100644 --- a/PassAllPC.cpp +++ b/PassAllPC.cpp @@ -19,13 +19,15 @@ #include "PassAllPC.h" #include "DMRDefines.h" +#include "Log.h" #include #include -CPassAllPC::CPassAllPC(const char* name, unsigned int slot) : +CPassAllPC::CPassAllPC(const char* name, unsigned int slot, bool trace) : m_name(name), -m_slot(slot) +m_slot(slot), +m_trace(trace) { assert(slot == 1U || slot == 2U); } @@ -36,12 +38,22 @@ CPassAllPC::~CPassAllPC() bool CPassAllPC::processRF(CDMRData& data) { - return process(data); + bool ret = process(data); + + if (m_trace) + LogDebug("Rule Trace,\tPassAllPC %s Slot=%u: %s", m_name, m_slot, ret ? "matched" : "not matched"); + + return ret; } bool CPassAllPC::processNet(CDMRData& data) { - return process(data); + bool ret = process(data); + + if (m_trace) + LogDebug("Rule Trace,\tPassAllPC %s Slot=%u: %s", m_name, m_slot, ret ? "matched" : "not matched"); + + return ret; } bool CPassAllPC::process(CDMRData& data) diff --git a/PassAllPC.h b/PassAllPC.h index cfb3afb..cee8729 100644 --- a/PassAllPC.h +++ b/PassAllPC.h @@ -24,7 +24,7 @@ class CPassAllPC : public IRewrite { public: - CPassAllPC(const char* name, unsigned int slot); + CPassAllPC(const char* name, unsigned int slot, bool trace); virtual ~CPassAllPC(); virtual bool processRF(CDMRData& data); @@ -33,6 +33,7 @@ public: private: const char* m_name; unsigned int m_slot; + bool m_trace; bool process(CDMRData& data); }; diff --git a/PassAllTG.cpp b/PassAllTG.cpp index ff5ad81..a11697d 100644 --- a/PassAllTG.cpp +++ b/PassAllTG.cpp @@ -19,13 +19,15 @@ #include "PassAllTG.h" #include "DMRDefines.h" +#include "Log.h" #include #include -CPassAllTG::CPassAllTG(const char* name, unsigned int slot) : +CPassAllTG::CPassAllTG(const char* name, unsigned int slot, bool trace) : m_name(name), -m_slot(slot) +m_slot(slot), +m_trace(trace) { assert(slot == 1U || slot == 2U); } @@ -36,12 +38,22 @@ CPassAllTG::~CPassAllTG() bool CPassAllTG::processRF(CDMRData& data) { - return process(data); + bool ret = process(data); + + if (m_trace) + LogDebug("Rule Trace,\tPassAllTG %s Slot=%u: %s", m_name, m_slot, ret ? "matched" : "not matched"); + + return ret; } bool CPassAllTG::processNet(CDMRData& data) { - return process(data); + bool ret = process(data); + + if (m_trace) + LogDebug("Rule Trace,\tPassAllTG %s Slot=%u: %s", m_name, m_slot, ret ? "matched" : "not matched"); + + return ret; } bool CPassAllTG::process(CDMRData& data) diff --git a/PassAllTG.h b/PassAllTG.h index e17d7b6..9780d61 100644 --- a/PassAllTG.h +++ b/PassAllTG.h @@ -24,7 +24,7 @@ class CPassAllTG : public IRewrite { public: - CPassAllTG(const char* name, unsigned int slot); + CPassAllTG(const char* name, unsigned int slot, bool trace); virtual ~CPassAllTG(); virtual bool processRF(CDMRData& data); @@ -33,6 +33,7 @@ public: private: const char* m_name; unsigned int m_slot; + bool m_trace; bool process(CDMRData& data); }; diff --git a/RewritePC.cpp b/RewritePC.cpp index e3b281e..b4f6246 100644 --- a/RewritePC.cpp +++ b/RewritePC.cpp @@ -20,17 +20,19 @@ #include "DMRDefines.h" #include "DMRFullLC.h" +#include "Log.h" #include #include -CRewritePC::CRewritePC(const char* name, unsigned int fromSlot, unsigned int fromId, unsigned int toSlot, unsigned int toId, unsigned int range) : +CRewritePC::CRewritePC(const char* name, unsigned int fromSlot, unsigned int fromId, unsigned int toSlot, unsigned int toId, unsigned int range, bool trace) : m_name(name), m_fromSlot(fromSlot), m_fromIdStart(fromId), m_fromIdEnd(fromId + range), m_toSlot(toSlot), m_toIdStart(toId), +m_trace(trace), m_lc(FLCO_USER_USER, 0U, 0U), m_embeddedLC() { @@ -44,12 +46,22 @@ CRewritePC::~CRewritePC() bool CRewritePC::processRF(CDMRData& data) { - return process(data); + bool ret = process(data); + + if (m_trace) + LogDebug("Rule Trace,\tRewritePC %s Slot=%u Dst=%u-%u: %s", m_name, m_fromSlot, m_fromIdStart, m_fromIdEnd, ret ? "matched" : "not matched"); + + return ret; } bool CRewritePC::processNet(CDMRData& data) { - return process(data); + bool ret = process(data); + + if (m_trace) + LogDebug("Rule Trace,\tRewritePC %s Slot=%u Dst=%u-%u: %s", m_name, m_fromSlot, m_fromIdStart, m_fromIdEnd, ret ? "matched" : "not matched"); + + return ret; } bool CRewritePC::process(CDMRData& data) diff --git a/RewritePC.h b/RewritePC.h index 550ad71..d5872c3 100644 --- a/RewritePC.h +++ b/RewritePC.h @@ -26,7 +26,7 @@ class CRewritePC : public IRewrite { public: - CRewritePC(const char* name, unsigned int fromSlot, unsigned int fromId, unsigned int toSlot, unsigned int toId, unsigned int range); + CRewritePC(const char* name, unsigned int fromSlot, unsigned int fromId, unsigned int toSlot, unsigned int toId, unsigned int range, bool trace); virtual ~CRewritePC(); virtual bool processRF(CDMRData& data); @@ -39,6 +39,7 @@ private: unsigned int m_fromIdEnd; unsigned int m_toSlot; unsigned int m_toIdStart; + bool m_trace; CDMRLC m_lc; CDMREmbeddedData m_embeddedLC; diff --git a/RewriteSrc.cpp b/RewriteSrc.cpp index 8aa9a62..5b470fe 100644 --- a/RewriteSrc.cpp +++ b/RewriteSrc.cpp @@ -25,13 +25,14 @@ #include #include -CRewriteSrc::CRewriteSrc(const char* name, unsigned int fromSlot, unsigned int fromId, unsigned int toSlot, unsigned int toTG, unsigned int range) : +CRewriteSrc::CRewriteSrc(const char* name, unsigned int fromSlot, unsigned int fromId, unsigned int toSlot, unsigned int toTG, unsigned int range, bool trace) : m_name(name), m_fromSlot(fromSlot), m_fromIdStart(fromId), m_fromIdEnd(fromId + range), m_toSlot(toSlot), m_toTG(toTG), +m_trace(trace), m_lc(FLCO_GROUP, 0U, toTG), m_embeddedLC() { @@ -47,12 +48,22 @@ CRewriteSrc::~CRewriteSrc() bool CRewriteSrc::processRF(CDMRData& data) { - return process(data); + bool ret = process(data); + + if (m_trace) + LogDebug("Rule Trace,\tRewriteSrc %s Slot=%u Src=%u-%u: %s", m_name, m_fromSlot, m_fromIdStart, m_fromIdEnd, ret ? "matched" : "not matched"); + + return ret; } bool CRewriteSrc::processNet(CDMRData& data) { - return process(data); + bool ret = process(data); + + if (m_trace) + LogDebug("Rule Trace,\tRewriteSrc %s Slot=%u Src=%u-%u: %s", m_name, m_fromSlot, m_fromIdStart, m_fromIdEnd, ret ? "matched" : "not matched"); + + return ret; } bool CRewriteSrc::process(CDMRData& data) diff --git a/RewriteSrc.h b/RewriteSrc.h index d68ef79..3bc2325 100644 --- a/RewriteSrc.h +++ b/RewriteSrc.h @@ -26,7 +26,7 @@ class CRewriteSrc : public IRewrite { public: - CRewriteSrc(const char* name, unsigned int fromSlot, unsigned int fromId, unsigned int toSlot, unsigned int toTG, unsigned int range); + CRewriteSrc(const char* name, unsigned int fromSlot, unsigned int fromId, unsigned int toSlot, unsigned int toTG, unsigned int range, bool trace); virtual ~CRewriteSrc(); virtual bool processRF(CDMRData& data); @@ -39,6 +39,7 @@ private: unsigned int m_fromIdEnd; unsigned int m_toSlot; unsigned int m_toTG; + bool m_trace; CDMRLC m_lc; CDMREmbeddedData m_embeddedLC; diff --git a/RewriteTG.cpp b/RewriteTG.cpp index 8f44e4a..1b005e9 100644 --- a/RewriteTG.cpp +++ b/RewriteTG.cpp @@ -20,17 +20,19 @@ #include "DMRDefines.h" #include "DMRFullLC.h" +#include "Log.h" #include #include -CRewriteTG::CRewriteTG(const char* name, unsigned int fromSlot, unsigned int fromTG, unsigned int toSlot, unsigned int toTG, unsigned int range) : +CRewriteTG::CRewriteTG(const char* name, unsigned int fromSlot, unsigned int fromTG, unsigned int toSlot, unsigned int toTG, unsigned int range, bool trace) : m_name(name), m_fromSlot(fromSlot), m_fromTGStart(fromTG), m_fromTGEnd(fromTG + range), m_toSlot(toSlot), m_toTGStart(toTG), +m_trace(trace), m_lc(FLCO_GROUP, 0U, toTG), m_embeddedLC() { @@ -44,18 +46,28 @@ CRewriteTG::~CRewriteTG() bool CRewriteTG::processRF(CDMRData& data) { - return process(data); + bool ret = process(data); + + if (m_trace) + LogDebug("Rule Trace,\tRewriteTG %s Slot=%u Dst=TG%u-TG%u: %s", m_name, m_fromSlot, m_fromTGStart, m_fromTGEnd, ret ? "matched" : "not matched"); + + return ret; } bool CRewriteTG::processNet(CDMRData& data) { - return process(data); + bool ret = process(data); + + if (m_trace) + LogDebug("Rule Trace,\tRewriteTG %s Slot=%u Dst=TG%u-TG%u: %s", m_name, m_fromSlot, m_fromTGStart, m_fromTGEnd, ret ? "matched" : "not matched"); + + return ret; } bool CRewriteTG::process(CDMRData& data) { - FLCO flco = data.getFLCO(); - unsigned int dstId = data.getDstId(); + FLCO flco = data.getFLCO(); + unsigned int dstId = data.getDstId(); unsigned int slotNo = data.getSlotNo(); if (flco != FLCO_GROUP || slotNo != m_fromSlot || dstId < m_fromTGStart || dstId >= m_fromTGEnd) diff --git a/RewriteTG.h b/RewriteTG.h index 5f2a7f8..1b61799 100644 --- a/RewriteTG.h +++ b/RewriteTG.h @@ -26,7 +26,7 @@ class CRewriteTG : public IRewrite { public: - CRewriteTG(const char*name, unsigned int fromSlot, unsigned int fromTG, unsigned int toSlot, unsigned int toTG, unsigned int range); + CRewriteTG(const char*name, unsigned int fromSlot, unsigned int fromTG, unsigned int toSlot, unsigned int toTG, unsigned int range, bool trace); virtual ~CRewriteTG(); virtual bool processRF(CDMRData& data); @@ -39,6 +39,7 @@ private: unsigned int m_fromTGEnd; unsigned int m_toSlot; unsigned int m_toTGStart; + bool m_trace; CDMRLC m_lc; CDMREmbeddedData m_embeddedLC; diff --git a/RewriteType.cpp b/RewriteType.cpp index a3936da..6f277cf 100644 --- a/RewriteType.cpp +++ b/RewriteType.cpp @@ -25,12 +25,13 @@ #include #include -CRewriteType::CRewriteType(const char* name, unsigned int fromSlot, unsigned int fromTG, unsigned int toSlot, unsigned int toId) : +CRewriteType::CRewriteType(const char* name, unsigned int fromSlot, unsigned int fromTG, unsigned int toSlot, unsigned int toId, bool trace) : m_name(name), m_fromSlot(fromSlot), m_fromTG(fromTG), m_toSlot(toSlot), m_toId(toId), +m_trace(trace), m_lc(FLCO_USER_USER, 0U, toId), m_embeddedLC() { @@ -44,18 +45,28 @@ CRewriteType::~CRewriteType() bool CRewriteType::processRF(CDMRData& data) { - return process(data); + bool ret = process(data); + + if (m_trace) + LogDebug("Rule Trace,\tRewriteType %s Slot=%u Dst=TG%u: %s", m_name, m_fromSlot, m_fromTG, ret ? "matched" : "not matched"); + + return ret; } bool CRewriteType::processNet(CDMRData& data) { - return process(data); + bool ret = process(data); + + if (m_trace) + LogDebug("Rule Trace,\tRewriteType %s Slot=%u Dst=TG%u: %s", m_name, m_fromSlot, m_fromTG, ret ? "matched" : "not matched"); + + return ret; } bool CRewriteType::process(CDMRData& data) { - FLCO flco = data.getFLCO(); - unsigned int dstId = data.getDstId(); + FLCO flco = data.getFLCO(); + unsigned int dstId = data.getDstId(); unsigned int slotNo = data.getSlotNo(); if (flco != FLCO_GROUP || slotNo != m_fromSlot || dstId != m_fromTG) diff --git a/RewriteType.h b/RewriteType.h index c8de2f2..ccac537 100644 --- a/RewriteType.h +++ b/RewriteType.h @@ -26,7 +26,7 @@ class CRewriteType : public IRewrite { public: - CRewriteType(const char* name, unsigned int fromSlot, unsigned int fromTG, unsigned int toSlot, unsigned int toId); + CRewriteType(const char* name, unsigned int fromSlot, unsigned int fromTG, unsigned int toSlot, unsigned int toId, bool trace); virtual ~CRewriteType(); virtual bool processRF(CDMRData& data); @@ -38,6 +38,7 @@ private: unsigned int m_fromTG; unsigned int m_toSlot; unsigned int m_toId; + bool m_trace; CDMRLC m_lc; CDMREmbeddedData m_embeddedLC; From 7cd557de8af31a01687445460e0c00d1b9b95562 Mon Sep 17 00:00:00 2001 From: Jonathan Naylor Date: Sun, 4 Jun 2017 19:12:16 +0100 Subject: [PATCH 09/20] Fix bug in tracing code, now enabled correctly. --- DMRGateway.cpp | 69 +++++++++++++++++++++++++------------------------- DMRGateway.h | 5 ++-- 2 files changed, 36 insertions(+), 38 deletions(-) diff --git a/DMRGateway.cpp b/DMRGateway.cpp index ae940a6..f7ad49c 100644 --- a/DMRGateway.cpp +++ b/DMRGateway.cpp @@ -127,7 +127,6 @@ int main(int argc, char** argv) CDMRGateway::CDMRGateway(const std::string& confFile) : m_conf(confFile), -m_ruleTrace(false), m_repeater(NULL), m_dmrNetwork1(NULL), m_dmrNetwork2(NULL), @@ -286,14 +285,17 @@ int CDMRGateway::run() LogMessage("MMDVM has connected"); + bool ruleTrace = m_conf.getRuleTrace(); + LogInfo("Rule trace: %s", ruleTrace ? "yes" : "no"); + if (m_conf.getDMRNetwork1Enabled()) { - ret = createDMRNetwork1(); + ret = createDMRNetwork1(ruleTrace); if (!ret) return 1; } if (m_conf.getDMRNetwork2Enabled()) { - ret = createDMRNetwork2(); + ret = createDMRNetwork2(ruleTrace); if (!ret) return 1; } @@ -343,9 +345,6 @@ int CDMRGateway::run() } } - m_ruleTrace = m_conf.getRuleTrace(); - LogInfo("Rule trace: %s", m_ruleTrace ? "yes" : "no"); - CTimer* timer[3U]; timer[1U] = new CTimer(1000U, timeout); timer[2U] = new CTimer(1000U, timeout); @@ -517,8 +516,8 @@ int CDMRGateway::run() unsigned int dstId = data.getDstId(); FLCO flco = data.getFLCO(); - if (m_ruleTrace) - LogDebug("Rule Trace, RF transmission: S%u %u -> %s%u", slotNo, srcId, flco == FLCO_GROUP ? "TG" : "", dstId); + if (ruleTrace) + LogDebug("Rule Trace, RF transmission: Slot=%u Src=%u Dst=%s%u", slotNo, srcId, flco == FLCO_GROUP ? "TG" : "", dstId); bool rewritten = false; @@ -562,7 +561,7 @@ int CDMRGateway::run() } } - if (!rewritten && m_ruleTrace) + if (!rewritten && ruleTrace) LogDebug("Rule Trace,\tnot matched so rejected"); } } @@ -614,8 +613,8 @@ int CDMRGateway::run() unsigned int dstId = data.getDstId(); FLCO flco = data.getFLCO(); - if (m_ruleTrace) - LogDebug("Rule Trace, network 1 transmission: S%u %u -> %s%u", slotNo, srcId, flco == FLCO_GROUP ? "TG" : "", dstId); + if (ruleTrace) + LogDebug("Rule Trace, network 1 transmission: Slot=%u Src=%u Dst=%s%u", slotNo, srcId, flco == FLCO_GROUP ? "TG" : "", dstId); // Rewrite the slot and/or TG or neither bool rewritten = false; @@ -635,7 +634,7 @@ int CDMRGateway::run() } } - if (!rewritten && m_ruleTrace) + if (!rewritten && ruleTrace) LogDebug("Rule Trace,\tnot matched so rejected"); } @@ -652,8 +651,8 @@ int CDMRGateway::run() unsigned int dstId = data.getDstId(); FLCO flco = data.getFLCO(); - if (m_ruleTrace) - LogDebug("Rule Trace, network 2 transmission: S%u %u -> %s%u", slotNo, srcId, flco == FLCO_GROUP ? "TG" : "", dstId); + if (ruleTrace) + LogDebug("Rule Trace, network 2 transmission: Slot=%u Src=%u Dst=%s%u", slotNo, srcId, flco == FLCO_GROUP ? "TG" : "", dstId); // Rewrite the slot and/or TG or neither bool rewritten = false; @@ -673,7 +672,7 @@ int CDMRGateway::run() } } - if (!rewritten && m_ruleTrace) + if (!rewritten && ruleTrace) LogDebug("Rule Trace,\tnot matched so rejected"); } @@ -820,7 +819,7 @@ bool CDMRGateway::createMMDVM() return true; } -bool CDMRGateway::createDMRNetwork1() +bool CDMRGateway::createDMRNetwork1(bool trace) { std::string address = m_conf.getDMRNetwork1Address(); unsigned int port = m_conf.getDMRNetwork1Port(); @@ -869,8 +868,8 @@ bool CDMRGateway::createDMRNetwork1() LogInfo(" Rewrite RF: %u:TG%u-TG%u -> %u:TG%u-TG%u", (*it).m_fromSlot, (*it).m_fromTG, (*it).m_fromTG + (*it).m_range - 1U, (*it).m_toSlot, (*it).m_toTG, (*it).m_toTG + (*it).m_range - 1U); LogInfo(" Rewrite Net: %u:TG%u-TG%u -> %u:TG%u-TG%u", (*it).m_toSlot, (*it).m_toTG, (*it).m_toTG + (*it).m_range - 1U, (*it).m_fromSlot, (*it).m_fromTG, (*it).m_fromTG + (*it).m_range - 1U); - CRewriteTG* rfRewrite = new CRewriteTG("DMR-1", (*it).m_fromSlot, (*it).m_fromTG, (*it).m_toSlot, (*it).m_toTG, (*it).m_range, m_ruleTrace); - CRewriteTG* netRewrite = new CRewriteTG("DMR-1", (*it).m_toSlot, (*it).m_toTG, (*it).m_fromSlot, (*it).m_fromTG, (*it).m_range, m_ruleTrace); + CRewriteTG* rfRewrite = new CRewriteTG("DMR-1", (*it).m_fromSlot, (*it).m_fromTG, (*it).m_toSlot, (*it).m_toTG, (*it).m_range, trace); + CRewriteTG* netRewrite = new CRewriteTG("DMR-1", (*it).m_toSlot, (*it).m_toTG, (*it).m_fromSlot, (*it).m_fromTG, (*it).m_range, trace); m_dmr1RFRewrites.push_back(rfRewrite); m_dmr1NetRewrites.push_back(netRewrite); @@ -880,7 +879,7 @@ bool CDMRGateway::createDMRNetwork1() for (std::vector::const_iterator it = pcRewrites.begin(); it != pcRewrites.end(); ++it) { LogInfo(" Rewrite RF: %u:%u-%u -> %u:%u-%u", (*it).m_fromSlot, (*it).m_fromId, (*it).m_fromId + (*it).m_range - 1U, (*it).m_toSlot, (*it).m_toId, (*it).m_toId + (*it).m_range - 1U); - CRewritePC* rewrite = new CRewritePC("DMR-1", (*it).m_fromSlot, (*it).m_fromId, (*it).m_toSlot, (*it).m_toId, (*it).m_range, m_ruleTrace); + CRewritePC* rewrite = new CRewritePC("DMR-1", (*it).m_fromSlot, (*it).m_fromId, (*it).m_toSlot, (*it).m_toId, (*it).m_range, trace); m_dmr1RFRewrites.push_back(rewrite); } @@ -889,7 +888,7 @@ bool CDMRGateway::createDMRNetwork1() for (std::vector::const_iterator it = typeRewrites.begin(); it != typeRewrites.end(); ++it) { LogInfo(" Rewrite RF: %u:TG%u -> %u:%u", (*it).m_fromSlot, (*it).m_fromTG, (*it).m_toSlot, (*it).m_toId); - CRewriteType* rewrite = new CRewriteType("DMR-1", (*it).m_fromSlot, (*it).m_fromTG, (*it).m_toSlot, (*it).m_toId, m_ruleTrace); + CRewriteType* rewrite = new CRewriteType("DMR-1", (*it).m_fromSlot, (*it).m_fromTG, (*it).m_toSlot, (*it).m_toId, trace); m_dmr1RFRewrites.push_back(rewrite); } @@ -898,7 +897,7 @@ bool CDMRGateway::createDMRNetwork1() for (std::vector::const_iterator it = srcRewrites.begin(); it != srcRewrites.end(); ++it) { LogInfo(" Rewrite Net: %u:%u-%u -> %u:TG%u", (*it).m_fromSlot, (*it).m_fromId, (*it).m_fromId + (*it).m_range - 1U, (*it).m_toSlot, (*it).m_toTG); - CRewriteSrc* rewrite = new CRewriteSrc("DMR-1", (*it).m_fromSlot, (*it).m_fromId, (*it).m_toSlot, (*it).m_toTG, (*it).m_range, m_ruleTrace); + CRewriteSrc* rewrite = new CRewriteSrc("DMR-1", (*it).m_fromSlot, (*it).m_fromId, (*it).m_toSlot, (*it).m_toTG, (*it).m_range, trace); m_dmr1NetRewrites.push_back(rewrite); } @@ -907,8 +906,8 @@ bool CDMRGateway::createDMRNetwork1() for (std::vector::const_iterator it = tgPassAll.begin(); it != tgPassAll.end(); ++it) { LogInfo(" Pass All TG: %u", *it); - CPassAllTG* rfPassAllTG = new CPassAllTG("DMR-1", *it, m_ruleTrace); - CPassAllTG* netPassAllTG = new CPassAllTG("DMR-1", *it, m_ruleTrace); + CPassAllTG* rfPassAllTG = new CPassAllTG("DMR-1", *it, trace); + CPassAllTG* netPassAllTG = new CPassAllTG("DMR-1", *it, trace); m_dmr1RFRewrites.push_back(rfPassAllTG); m_dmr1NetRewrites.push_back(netPassAllTG); @@ -918,8 +917,8 @@ bool CDMRGateway::createDMRNetwork1() for (std::vector::const_iterator it = pcPassAll.begin(); it != pcPassAll.end(); ++it) { LogInfo(" Pass All PC: %u", *it); - CPassAllPC* rfPassAllPC = new CPassAllPC("DMR-1", *it, m_ruleTrace); - CPassAllPC* netPassAllPC = new CPassAllPC("DMR-1", *it, m_ruleTrace); + CPassAllPC* rfPassAllPC = new CPassAllPC("DMR-1", *it, trace); + CPassAllPC* netPassAllPC = new CPassAllPC("DMR-1", *it, trace); m_dmr1RFRewrites.push_back(rfPassAllPC); m_dmr1NetRewrites.push_back(netPassAllPC); @@ -928,7 +927,7 @@ bool CDMRGateway::createDMRNetwork1() return true; } -bool CDMRGateway::createDMRNetwork2() +bool CDMRGateway::createDMRNetwork2(bool trace) { std::string address = m_conf.getDMRNetwork2Address(); unsigned int port = m_conf.getDMRNetwork2Port(); @@ -977,8 +976,8 @@ bool CDMRGateway::createDMRNetwork2() LogInfo(" Rewrite RF: %u:TG%u-TG%u -> %u:TG%u-TG%u", (*it).m_fromSlot, (*it).m_fromTG, (*it).m_fromTG + (*it).m_range - 1U, (*it).m_toSlot, (*it).m_toTG, (*it).m_toTG + (*it).m_range - 1U); LogInfo(" Rewrite Net: %u:TG%u-TG%u -> %u:TG%u-TG%u", (*it).m_toSlot, (*it).m_toTG, (*it).m_toTG + (*it).m_range - 1U, (*it).m_fromSlot, (*it).m_fromTG, (*it).m_fromTG + (*it).m_range - 1U); - CRewriteTG* rfRewrite = new CRewriteTG("DMR-2", (*it).m_fromSlot, (*it).m_fromTG, (*it).m_toSlot, (*it).m_toTG, (*it).m_range, m_ruleTrace); - CRewriteTG* netRewrite = new CRewriteTG("DMR-2", (*it).m_toSlot, (*it).m_toTG, (*it).m_fromSlot, (*it).m_fromTG, (*it).m_range, m_ruleTrace); + CRewriteTG* rfRewrite = new CRewriteTG("DMR-2", (*it).m_fromSlot, (*it).m_fromTG, (*it).m_toSlot, (*it).m_toTG, (*it).m_range, trace); + CRewriteTG* netRewrite = new CRewriteTG("DMR-2", (*it).m_toSlot, (*it).m_toTG, (*it).m_fromSlot, (*it).m_fromTG, (*it).m_range, trace); m_dmr2RFRewrites.push_back(rfRewrite); m_dmr2NetRewrites.push_back(netRewrite); @@ -988,7 +987,7 @@ bool CDMRGateway::createDMRNetwork2() for (std::vector::const_iterator it = pcRewrites.begin(); it != pcRewrites.end(); ++it) { LogInfo(" Rewrite RF: %u:%u-%u -> %u:%u-%u", (*it).m_fromSlot, (*it).m_fromId, (*it).m_fromId + (*it).m_range - 1U, (*it).m_toSlot, (*it).m_toId, (*it).m_toId + (*it).m_range - 1U); - CRewritePC* rewrite = new CRewritePC("DMR-2", (*it).m_fromSlot, (*it).m_fromId, (*it).m_toSlot, (*it).m_toId, (*it).m_range, m_ruleTrace); + CRewritePC* rewrite = new CRewritePC("DMR-2", (*it).m_fromSlot, (*it).m_fromId, (*it).m_toSlot, (*it).m_toId, (*it).m_range, trace); m_dmr2RFRewrites.push_back(rewrite); } @@ -997,7 +996,7 @@ bool CDMRGateway::createDMRNetwork2() for (std::vector::const_iterator it = typeRewrites.begin(); it != typeRewrites.end(); ++it) { LogInfo(" Rewrite RF: %u:TG%u -> %u:%u", (*it).m_fromSlot, (*it).m_fromTG, (*it).m_toSlot, (*it).m_toId); - CRewriteType* rewrite = new CRewriteType("DMR-2", (*it).m_fromSlot, (*it).m_fromTG, (*it).m_toSlot, (*it).m_toId, m_ruleTrace); + CRewriteType* rewrite = new CRewriteType("DMR-2", (*it).m_fromSlot, (*it).m_fromTG, (*it).m_toSlot, (*it).m_toId, trace); m_dmr2RFRewrites.push_back(rewrite); } @@ -1006,7 +1005,7 @@ bool CDMRGateway::createDMRNetwork2() for (std::vector::const_iterator it = srcRewrites.begin(); it != srcRewrites.end(); ++it) { LogInfo(" Rewrite Net: %u:%u-%u -> %u:TG%u", (*it).m_fromSlot, (*it).m_fromId, (*it).m_fromId + (*it).m_range - 1U, (*it).m_toSlot, (*it).m_toTG); - CRewriteSrc* rewrite = new CRewriteSrc("DMR-2", (*it).m_fromSlot, (*it).m_fromId, (*it).m_toSlot, (*it).m_toTG, (*it).m_range, m_ruleTrace); + CRewriteSrc* rewrite = new CRewriteSrc("DMR-2", (*it).m_fromSlot, (*it).m_fromId, (*it).m_toSlot, (*it).m_toTG, (*it).m_range, trace); m_dmr2NetRewrites.push_back(rewrite); } @@ -1015,8 +1014,8 @@ bool CDMRGateway::createDMRNetwork2() for (std::vector::const_iterator it = tgPassAll.begin(); it != tgPassAll.end(); ++it) { LogInfo(" Pass All TG: %u", *it); - CPassAllTG* rfPassAllTG = new CPassAllTG("DMR-2", *it, m_ruleTrace); - CPassAllTG* netPassAllTG = new CPassAllTG("DMR-2", *it, m_ruleTrace); + CPassAllTG* rfPassAllTG = new CPassAllTG("DMR-2", *it, trace); + CPassAllTG* netPassAllTG = new CPassAllTG("DMR-2", *it, trace); m_dmr2RFRewrites.push_back(rfPassAllTG); m_dmr2NetRewrites.push_back(netPassAllTG); @@ -1026,8 +1025,8 @@ bool CDMRGateway::createDMRNetwork2() for (std::vector::const_iterator it = pcPassAll.begin(); it != pcPassAll.end(); ++it) { LogInfo(" Pass All PC: %u", *it); - CPassAllPC* rfPassAllPC = new CPassAllPC("DMR-2", *it, m_ruleTrace); - CPassAllPC* netPassAllPC = new CPassAllPC("DMR-2", *it, m_ruleTrace); + CPassAllPC* rfPassAllPC = new CPassAllPC("DMR-2", *it, trace); + CPassAllPC* netPassAllPC = new CPassAllPC("DMR-2", *it, trace); m_dmr2RFRewrites.push_back(rfPassAllPC); m_dmr2NetRewrites.push_back(netPassAllPC); diff --git a/DMRGateway.h b/DMRGateway.h index bae8be1..ab2bfd2 100644 --- a/DMRGateway.h +++ b/DMRGateway.h @@ -38,7 +38,6 @@ public: private: CConf m_conf; - bool m_ruleTrace; IRepeaterProtocol* m_repeater; CDMRNetwork* m_dmrNetwork1; CDMRNetwork* m_dmrNetwork2; @@ -68,8 +67,8 @@ private: std::vector m_dmr2RFRewrites; bool createMMDVM(); - bool createDMRNetwork1(); - bool createDMRNetwork2(); + bool createDMRNetwork1(bool trace); + bool createDMRNetwork2(bool trace); bool createXLXNetwork1(); bool createXLXNetwork2(); void writeXLXLink(unsigned int srcId, unsigned int dstId, CDMRNetwork* network); From 2d670d330bcc9d2ec2ad2b7108e89b3db7a01308 Mon Sep 17 00:00:00 2001 From: Tony Corbett G0WFV Date: Wed, 7 Jun 2017 10:38:53 +0100 Subject: [PATCH 10/20] Alter rewrite ranges so they appear correctly in tracing --- RewritePC.cpp | 4 ++-- RewriteSrc.cpp | 4 ++-- RewriteTG.cpp | 4 ++-- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/RewritePC.cpp b/RewritePC.cpp index b4f6246..f3fb65a 100644 --- a/RewritePC.cpp +++ b/RewritePC.cpp @@ -29,7 +29,7 @@ CRewritePC::CRewritePC(const char* name, unsigned int fromSlot, unsigned int fro m_name(name), m_fromSlot(fromSlot), m_fromIdStart(fromId), -m_fromIdEnd(fromId + range), +m_fromIdEnd(fromId + range - 1U), m_toSlot(toSlot), m_toIdStart(toId), m_trace(trace), @@ -70,7 +70,7 @@ bool CRewritePC::process(CDMRData& data) unsigned int dstId = data.getDstId(); unsigned int slotNo = data.getSlotNo(); - if (flco != FLCO_USER_USER || slotNo != m_fromSlot || dstId < m_fromIdStart || dstId >= m_fromIdEnd) + if (flco != FLCO_USER_USER || slotNo != m_fromSlot || dstId < m_fromIdStart || dstId > m_fromIdEnd) return false; if (m_fromSlot != m_toSlot) diff --git a/RewriteSrc.cpp b/RewriteSrc.cpp index 5b470fe..71541fc 100644 --- a/RewriteSrc.cpp +++ b/RewriteSrc.cpp @@ -29,7 +29,7 @@ CRewriteSrc::CRewriteSrc(const char* name, unsigned int fromSlot, unsigned int f m_name(name), m_fromSlot(fromSlot), m_fromIdStart(fromId), -m_fromIdEnd(fromId + range), +m_fromIdEnd(fromId + range - 1U), m_toSlot(toSlot), m_toTG(toTG), m_trace(trace), @@ -72,7 +72,7 @@ bool CRewriteSrc::process(CDMRData& data) unsigned int srcId = data.getSrcId(); unsigned int slotNo = data.getSlotNo(); - if (flco != FLCO_USER_USER || slotNo != m_fromSlot || srcId < m_fromIdStart || srcId >= m_fromIdEnd) + if (flco != FLCO_USER_USER || slotNo != m_fromSlot || srcId < m_fromIdStart || srcId > m_fromIdEnd) return false; if (m_fromSlot != m_toSlot) diff --git a/RewriteTG.cpp b/RewriteTG.cpp index 1b005e9..6c4cfac 100644 --- a/RewriteTG.cpp +++ b/RewriteTG.cpp @@ -29,7 +29,7 @@ CRewriteTG::CRewriteTG(const char* name, unsigned int fromSlot, unsigned int fro m_name(name), m_fromSlot(fromSlot), m_fromTGStart(fromTG), -m_fromTGEnd(fromTG + range), +m_fromTGEnd(fromTG + range - 1U), m_toSlot(toSlot), m_toTGStart(toTG), m_trace(trace), @@ -70,7 +70,7 @@ bool CRewriteTG::process(CDMRData& data) unsigned int dstId = data.getDstId(); unsigned int slotNo = data.getSlotNo(); - if (flco != FLCO_GROUP || slotNo != m_fromSlot || dstId < m_fromTGStart || dstId >= m_fromTGEnd) + if (flco != FLCO_GROUP || slotNo != m_fromSlot || dstId < m_fromTGStart || dstId > m_fromTGEnd) return false; if (m_fromSlot != m_toSlot) From e4b3f2b6cbc307dd2a7c0f8685c5ba934825ea96 Mon Sep 17 00:00:00 2001 From: g0wfv Date: Wed, 7 Jun 2017 13:15:17 +0100 Subject: [PATCH 11/20] Add an extra trace line when matched to say where rewritten to --- RewritePC.cpp | 11 +++++++++-- RewritePC.h | 1 + RewriteSrc.cpp | 10 ++++++++-- RewriteTG.cpp | 11 +++++++++-- RewriteTG.h | 1 + 5 files changed, 28 insertions(+), 6 deletions(-) diff --git a/RewritePC.cpp b/RewritePC.cpp index f3fb65a..2f76aea 100644 --- a/RewritePC.cpp +++ b/RewritePC.cpp @@ -32,6 +32,7 @@ m_fromIdStart(fromId), m_fromIdEnd(fromId + range - 1U), m_toSlot(toSlot), m_toIdStart(toId), +m_toIdEnd(toId + range - 1U), m_trace(trace), m_lc(FLCO_USER_USER, 0U, 0U), m_embeddedLC() @@ -49,7 +50,10 @@ bool CRewritePC::processRF(CDMRData& data) bool ret = process(data); if (m_trace) - LogDebug("Rule Trace,\tRewritePC %s Slot=%u Dst=%u-%u: %s", m_name, m_fromSlot, m_fromIdStart, m_fromIdEnd, ret ? "matched" : "not matched"); + LogDebug("Rule Trace,\tRewritePC from %s Slot=%u Dst=%u-%u: %s", m_name, m_fromSlot, m_fromIdStart, m_fromIdEnd, ret ? "matched" : "not matched"); + + if (m_trace && ret) + LogDebug("Rule Trace,\tRewritePC to %s Slot=%u Dst=%u-%u", m_name, m_toSlot, m_toIdStart, m_toIdEnd); return ret; } @@ -59,7 +63,10 @@ bool CRewritePC::processNet(CDMRData& data) bool ret = process(data); if (m_trace) - LogDebug("Rule Trace,\tRewritePC %s Slot=%u Dst=%u-%u: %s", m_name, m_fromSlot, m_fromIdStart, m_fromIdEnd, ret ? "matched" : "not matched"); + LogDebug("Rule Trace,\tRewritePC from %s Slot=%u Dst=%u-%u: %s", m_name, m_fromSlot, m_fromIdStart, m_fromIdEnd, ret ? "matched" : "not matched"); + + if (m_trace && ret) + LogDebug("Rule Trace,\tRewritePC to %s Slot=%u Dst=%u-%u", m_name, m_toSlot, m_toIdStart, m_toIdEnd); return ret; } diff --git a/RewritePC.h b/RewritePC.h index d5872c3..0379a12 100644 --- a/RewritePC.h +++ b/RewritePC.h @@ -39,6 +39,7 @@ private: unsigned int m_fromIdEnd; unsigned int m_toSlot; unsigned int m_toIdStart; + unsigned int m_toIdEnd; bool m_trace; CDMRLC m_lc; CDMREmbeddedData m_embeddedLC; diff --git a/RewriteSrc.cpp b/RewriteSrc.cpp index 71541fc..e9c8f3e 100644 --- a/RewriteSrc.cpp +++ b/RewriteSrc.cpp @@ -51,7 +51,10 @@ bool CRewriteSrc::processRF(CDMRData& data) bool ret = process(data); if (m_trace) - LogDebug("Rule Trace,\tRewriteSrc %s Slot=%u Src=%u-%u: %s", m_name, m_fromSlot, m_fromIdStart, m_fromIdEnd, ret ? "matched" : "not matched"); + LogDebug("Rule Trace,\tRewriteSrc from %s Slot=%u Src=%u-%u: %s", m_name, m_fromSlot, m_fromIdStart, m_fromIdEnd, ret ? "matched" : "not matched"); + + if (m_trace && ret) + LogDebug("Rule Trace,\tRewriteSrc to %s Slot=%u Dst=TG%u", m_name, m_toSlot, m_toTG); return ret; } @@ -61,7 +64,10 @@ bool CRewriteSrc::processNet(CDMRData& data) bool ret = process(data); if (m_trace) - LogDebug("Rule Trace,\tRewriteSrc %s Slot=%u Src=%u-%u: %s", m_name, m_fromSlot, m_fromIdStart, m_fromIdEnd, ret ? "matched" : "not matched"); + LogDebug("Rule Trace,\tRewriteSrc from %s Slot=%u Src=%u-%u: %s", m_name, m_fromSlot, m_fromIdStart, m_fromIdEnd, ret ? "matched" : "not matched"); + + if (m_trace && ret) + LogDebug("Rule Trace,\tRewriteSrc to %s Slot=%u Dst=TG%u", m_name, m_toSlot, m_toTG); return ret; } diff --git a/RewriteTG.cpp b/RewriteTG.cpp index 6c4cfac..63e3693 100644 --- a/RewriteTG.cpp +++ b/RewriteTG.cpp @@ -32,6 +32,7 @@ m_fromTGStart(fromTG), m_fromTGEnd(fromTG + range - 1U), m_toSlot(toSlot), m_toTGStart(toTG), +m_toTGEnd(toTG + range - 1U), m_trace(trace), m_lc(FLCO_GROUP, 0U, toTG), m_embeddedLC() @@ -49,7 +50,10 @@ bool CRewriteTG::processRF(CDMRData& data) bool ret = process(data); if (m_trace) - LogDebug("Rule Trace,\tRewriteTG %s Slot=%u Dst=TG%u-TG%u: %s", m_name, m_fromSlot, m_fromTGStart, m_fromTGEnd, ret ? "matched" : "not matched"); + LogDebug("Rule Trace,\tRewriteTG from %s Slot=%u Dst=TG%u-TG%u: %s", m_name, m_fromSlot, m_fromTGStart, m_fromTGEnd, ret ? "matched" : "not matched"); + + if (m_trace && ret) + LogDebug("Rule Trace,\tRewriteTG to %s Slot=%u Dst=TG%u-TG%u", m_name, m_toSlot, m_toTGStart, m_toTGEnd); return ret; } @@ -59,7 +63,10 @@ bool CRewriteTG::processNet(CDMRData& data) bool ret = process(data); if (m_trace) - LogDebug("Rule Trace,\tRewriteTG %s Slot=%u Dst=TG%u-TG%u: %s", m_name, m_fromSlot, m_fromTGStart, m_fromTGEnd, ret ? "matched" : "not matched"); + LogDebug("Rule Trace,\tRewriteTG from %s Slot=%u Dst=TG%u-TG%u: %s", m_name, m_fromSlot, m_fromTGStart, m_fromTGEnd, ret ? "matched" : "not matched"); + + if (m_trace && ret) + LogDebug("Rule Trace,\tRewriteTG to %s Slot=%u Dst=TG%u-TG%u", m_name, m_toSlot, m_toTGStart, m_toTGEnd); return ret; } diff --git a/RewriteTG.h b/RewriteTG.h index 1b61799..3db2266 100644 --- a/RewriteTG.h +++ b/RewriteTG.h @@ -39,6 +39,7 @@ private: unsigned int m_fromTGEnd; unsigned int m_toSlot; unsigned int m_toTGStart; + unsigned int m_toTGEnd; bool m_trace; CDMRLC m_lc; CDMREmbeddedData m_embeddedLC; From 64b3f0848c62462499b6914f02cefd649faf2d2b Mon Sep 17 00:00:00 2001 From: g0wfv Date: Wed, 7 Jun 2017 19:34:18 +0100 Subject: [PATCH 12/20] Add SIGINT handling and alter termination signal logging --- DMRGateway.cpp | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/DMRGateway.cpp b/DMRGateway.cpp index f7ad49c..080b65e 100644 --- a/DMRGateway.cpp +++ b/DMRGateway.cpp @@ -99,6 +99,7 @@ int main(int argc, char** argv) } #if !defined(_WIN32) && !defined(_WIN64) + ::signal(SIGINT, sigHandler); ::signal(SIGTERM, sigHandler); ::signal(SIGHUP, sigHandler); #endif @@ -113,11 +114,14 @@ int main(int argc, char** argv) delete host; + if (m_signal == 2) + ::LogInfo("DMRGateway-%s exited on receipt of SIGINT", VERSION); + if (m_signal == 15) - ::LogInfo("Caught SIGTERM, exiting"); + ::LogInfo("DMRGateway-%s exited on receipt of SIGTERM", VERSION); if (m_signal == 1) - ::LogInfo("Caught SIGHUP, restarting"); + ::LogInfo("DMRGateway-%s restarted on receipt of SIGHUP", VERSION); } while (m_signal == 1); ::LogFinalise(); @@ -277,7 +281,7 @@ int CDMRGateway::run() } if (m_killed) { - LogMessage("DMRGateway-%s is exiting on receipt of SIGHUP1", VERSION); +// LogMessage("DMRGateway-%s is exiting on receipt of SIGHUP1", VERSION); m_repeater->close(); delete m_repeater; return 0; @@ -759,7 +763,7 @@ int CDMRGateway::run() CThread::sleep(10U); } - LogMessage("DMRGateway-%s is exiting on receipt of SIGHUP1", VERSION); +// LogMessage("DMRGateway-%s is exiting on receipt of SIGHUP1", VERSION); delete voice1; delete voice2; From e1d0a469ebe1af7fe418135c283e6e9252fb8d6e Mon Sep 17 00:00:00 2001 From: g0wfv Date: Wed, 7 Jun 2017 19:52:31 +0100 Subject: [PATCH 13/20] Alert the host of shutdown by sending MSTNAK on network close --- MMDVMNetwork.cpp | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/MMDVMNetwork.cpp b/MMDVMNetwork.cpp index aadc537..fc360a6 100644 --- a/MMDVMNetwork.cpp +++ b/MMDVMNetwork.cpp @@ -255,9 +255,21 @@ bool CMMDVMNetwork::writeBeacon() void CMMDVMNetwork::close() { + unsigned char buffer[HOMEBREW_DATA_PACKET_LENGTH]; + ::memset(buffer, 0x00U, HOMEBREW_DATA_PACKET_LENGTH); + LogMessage("DMR, Closing MMDVM Network"); + buffer[0U] = 'M'; + buffer[1U] = 'S'; + buffer[2U] = 'T'; + buffer[3U] = 'N'; + buffer[4U] = 'A'; + buffer[5U] = 'K'; + + m_socket.write(buffer, HOMEBREW_DATA_PACKET_LENGTH, m_rptAddress, m_rptPort); m_socket.close(); + } void CMMDVMNetwork::clock(unsigned int ms) From 06a8b203ce13230cab2acb6ab163623e1e5a6531 Mon Sep 17 00:00:00 2001 From: Jonathan Naylor Date: Wed, 7 Jun 2017 20:40:51 +0100 Subject: [PATCH 14/20] Move the RF passall processing after all of the other rewrites are done. --- DMRGateway.cpp | 60 ++++++++++++++++++++++++++++++++++++++++++++------ DMRGateway.h | 2 ++ 2 files changed, 55 insertions(+), 7 deletions(-) diff --git a/DMRGateway.cpp b/DMRGateway.cpp index 080b65e..3f035b7 100644 --- a/DMRGateway.cpp +++ b/DMRGateway.cpp @@ -157,7 +157,9 @@ m_xlx2Rewrite(NULL), m_dmr1NetRewrites(), m_dmr1RFRewrites(), m_dmr2NetRewrites(), -m_dmr2RFRewrites() +m_dmr2RFRewrites(), +m_dmr1Passalls(), +m_dmr2Passalls() { } @@ -175,6 +177,12 @@ CDMRGateway::~CDMRGateway() for (std::vector::iterator it = m_dmr2RFRewrites.begin(); it != m_dmr2RFRewrites.end(); ++it) delete *it; + for (std::vector::iterator it = m_dmr1Passalls.begin(); it != m_dmr1Passalls.end(); ++it) + delete *it; + + for (std::vector::iterator it = m_dmr2Passalls.begin(); it != m_dmr2Passalls.end(); ++it) + delete *it; + delete m_rpt1Rewrite; delete m_xlx1Rewrite; delete m_rpt2Rewrite; @@ -565,6 +573,46 @@ int CDMRGateway::run() } } + if (!rewritten) { + if (m_dmrNetwork1 != NULL) { + for (std::vector::iterator it = m_dmr1Passalls.begin(); it != m_dmr1Passalls.end(); ++it) { + bool ret = (*it)->processRF(data); + if (ret) { + rewritten = true; + break; + } + } + + if (rewritten) { + if (status[slotNo] == DMRGWS_NONE || status[slotNo] == DMRGWS_DMRNETWORK1) { + m_dmrNetwork1->write(data); + status[slotNo] = DMRGWS_DMRNETWORK1; + timer[slotNo]->start(); + } + } + } + } + + if (!rewritten) { + if (m_dmrNetwork2 != NULL) { + for (std::vector::iterator it = m_dmr2Passalls.begin(); it != m_dmr2Passalls.end(); ++it) { + bool ret = (*it)->processRF(data); + if (ret) { + rewritten = true; + break; + } + } + + if (rewritten) { + if (status[slotNo] == DMRGWS_NONE || status[slotNo] == DMRGWS_DMRNETWORK2) { + m_dmrNetwork2->write(data); + status[slotNo] = DMRGWS_DMRNETWORK2; + timer[slotNo]->start(); + } + } + } + } + if (!rewritten && ruleTrace) LogDebug("Rule Trace,\tnot matched so rejected"); } @@ -763,8 +811,6 @@ int CDMRGateway::run() CThread::sleep(10U); } -// LogMessage("DMRGateway-%s is exiting on receipt of SIGHUP1", VERSION); - delete voice1; delete voice2; @@ -913,7 +959,7 @@ bool CDMRGateway::createDMRNetwork1(bool trace) CPassAllTG* rfPassAllTG = new CPassAllTG("DMR-1", *it, trace); CPassAllTG* netPassAllTG = new CPassAllTG("DMR-1", *it, trace); - m_dmr1RFRewrites.push_back(rfPassAllTG); + m_dmr1Passalls.push_back(rfPassAllTG); m_dmr1NetRewrites.push_back(netPassAllTG); } @@ -924,7 +970,7 @@ bool CDMRGateway::createDMRNetwork1(bool trace) CPassAllPC* rfPassAllPC = new CPassAllPC("DMR-1", *it, trace); CPassAllPC* netPassAllPC = new CPassAllPC("DMR-1", *it, trace); - m_dmr1RFRewrites.push_back(rfPassAllPC); + m_dmr1Passalls.push_back(rfPassAllPC); m_dmr1NetRewrites.push_back(netPassAllPC); } @@ -1021,7 +1067,7 @@ bool CDMRGateway::createDMRNetwork2(bool trace) CPassAllTG* rfPassAllTG = new CPassAllTG("DMR-2", *it, trace); CPassAllTG* netPassAllTG = new CPassAllTG("DMR-2", *it, trace); - m_dmr2RFRewrites.push_back(rfPassAllTG); + m_dmr2Passalls.push_back(rfPassAllTG); m_dmr2NetRewrites.push_back(netPassAllTG); } @@ -1032,7 +1078,7 @@ bool CDMRGateway::createDMRNetwork2(bool trace) CPassAllPC* rfPassAllPC = new CPassAllPC("DMR-2", *it, trace); CPassAllPC* netPassAllPC = new CPassAllPC("DMR-2", *it, trace); - m_dmr2RFRewrites.push_back(rfPassAllPC); + m_dmr2Passalls.push_back(rfPassAllPC); m_dmr2NetRewrites.push_back(netPassAllPC); } diff --git a/DMRGateway.h b/DMRGateway.h index ab2bfd2..fa35507 100644 --- a/DMRGateway.h +++ b/DMRGateway.h @@ -65,6 +65,8 @@ private: std::vector m_dmr1RFRewrites; std::vector m_dmr2NetRewrites; std::vector m_dmr2RFRewrites; + std::vector m_dmr1Passalls; + std::vector m_dmr2Passalls; bool createMMDVM(); bool createDMRNetwork1(bool trace); From 87bee93b2b470e6c0cf88a675e43eb524c9c1eac Mon Sep 17 00:00:00 2001 From: Jonathan Naylor Date: Wed, 7 Jun 2017 21:22:01 +0100 Subject: [PATCH 15/20] First stage of rationalising the rule tracing code. --- DMRGateway.cpp | 73 ++++++++++++++++++++++++------------------------- DMRGateway.h | 4 +-- PassAllPC.cpp | 34 ++++++----------------- PassAllPC.h | 8 ++---- PassAllTG.cpp | 34 ++++++----------------- PassAllTG.h | 8 ++---- Rewrite.h | 3 +- RewritePC.cpp | 41 ++++++++------------------- RewritePC.h | 7 ++--- RewriteSrc.cpp | 41 ++++++++------------------- RewriteSrc.h | 7 ++--- RewriteTG.cpp | 45 +++++++++--------------------- RewriteTG.h | 7 ++--- RewriteType.cpp | 33 ++++++---------------- RewriteType.h | 7 ++--- 15 files changed, 113 insertions(+), 239 deletions(-) diff --git a/DMRGateway.cpp b/DMRGateway.cpp index 3f035b7..9c16180 100644 --- a/DMRGateway.cpp +++ b/DMRGateway.cpp @@ -289,7 +289,6 @@ int CDMRGateway::run() } if (m_killed) { -// LogMessage("DMRGateway-%s is exiting on receipt of SIGHUP1", VERSION); m_repeater->close(); delete m_repeater; return 0; @@ -301,13 +300,13 @@ int CDMRGateway::run() LogInfo("Rule trace: %s", ruleTrace ? "yes" : "no"); if (m_conf.getDMRNetwork1Enabled()) { - ret = createDMRNetwork1(ruleTrace); + ret = createDMRNetwork1(); if (!ret) return 1; } if (m_conf.getDMRNetwork2Enabled()) { - ret = createDMRNetwork2(ruleTrace); + ret = createDMRNetwork2(); if (!ret) return 1; } @@ -431,12 +430,12 @@ int CDMRGateway::run() FLCO flco = data.getFLCO(); if (flco == FLCO_GROUP && slotNo == m_xlx1Slot && dstId == m_xlx1TG) { - m_xlx1Rewrite->processRF(data); + m_xlx1Rewrite->process(data, false); m_xlxNetwork1->write(data); status[slotNo] = DMRGWS_XLXREFLECTOR1; timer[slotNo]->start(); } else if (flco == FLCO_GROUP && slotNo == m_xlx2Slot && dstId == m_xlx2TG) { - m_xlx2Rewrite->processRF(data); + m_xlx2Rewrite->process(data, false); m_xlxNetwork2->write(data); status[slotNo] = DMRGWS_XLXREFLECTOR2; timer[slotNo]->start(); @@ -536,7 +535,7 @@ int CDMRGateway::run() if (m_dmrNetwork1 != NULL) { // Rewrite the slot and/or TG or neither for (std::vector::iterator it = m_dmr1RFRewrites.begin(); it != m_dmr1RFRewrites.end(); ++it) { - bool ret = (*it)->processRF(data); + bool ret = (*it)->process(data, ruleTrace); if (ret) { rewritten = true; break; @@ -556,7 +555,7 @@ int CDMRGateway::run() if (m_dmrNetwork2 != NULL) { // Rewrite the slot and/or TG or neither for (std::vector::iterator it = m_dmr2RFRewrites.begin(); it != m_dmr2RFRewrites.end(); ++it) { - bool ret = (*it)->processRF(data); + bool ret = (*it)->process(data, ruleTrace); if (ret) { rewritten = true; break; @@ -576,7 +575,7 @@ int CDMRGateway::run() if (!rewritten) { if (m_dmrNetwork1 != NULL) { for (std::vector::iterator it = m_dmr1Passalls.begin(); it != m_dmr1Passalls.end(); ++it) { - bool ret = (*it)->processRF(data); + bool ret = (*it)->process(data, ruleTrace); if (ret) { rewritten = true; break; @@ -596,7 +595,7 @@ int CDMRGateway::run() if (!rewritten) { if (m_dmrNetwork2 != NULL) { for (std::vector::iterator it = m_dmr2Passalls.begin(); it != m_dmr2Passalls.end(); ++it) { - bool ret = (*it)->processRF(data); + bool ret = (*it)->process(data, ruleTrace); if (ret) { rewritten = true; break; @@ -622,7 +621,7 @@ int CDMRGateway::run() ret = m_xlxNetwork1->read(data); if (ret) { if (status[m_xlx1Slot] == DMRGWS_NONE || status[m_xlx1Slot] == DMRGWS_XLXREFLECTOR1) { - bool ret = m_rpt1Rewrite->processNet(data); + bool ret = m_rpt1Rewrite->process(data, false); if (ret) { m_repeater->write(data); status[m_xlx1Slot] = DMRGWS_XLXREFLECTOR1; @@ -641,7 +640,7 @@ int CDMRGateway::run() ret = m_xlxNetwork2->read(data); if (ret) { if (status[m_xlx2Slot] == DMRGWS_NONE || status[m_xlx2Slot] == DMRGWS_XLXREFLECTOR2) { - bool ret = m_rpt2Rewrite->processNet(data); + bool ret = m_rpt2Rewrite->process(data, false); if (ret) { m_repeater->write(data); status[m_xlx2Slot] = DMRGWS_XLXREFLECTOR2; @@ -671,7 +670,7 @@ int CDMRGateway::run() // Rewrite the slot and/or TG or neither bool rewritten = false; for (std::vector::iterator it = m_dmr1NetRewrites.begin(); it != m_dmr1NetRewrites.end(); ++it) { - bool ret = (*it)->processNet(data); + bool ret = (*it)->process(data, ruleTrace); if (ret) { rewritten = true; break; @@ -709,7 +708,7 @@ int CDMRGateway::run() // Rewrite the slot and/or TG or neither bool rewritten = false; for (std::vector::iterator it = m_dmr2NetRewrites.begin(); it != m_dmr2NetRewrites.end(); ++it) { - bool ret = (*it)->processNet(data); + bool ret = (*it)->process(data, ruleTrace); if (ret) { rewritten = true; break; @@ -869,7 +868,7 @@ bool CDMRGateway::createMMDVM() return true; } -bool CDMRGateway::createDMRNetwork1(bool trace) +bool CDMRGateway::createDMRNetwork1() { std::string address = m_conf.getDMRNetwork1Address(); unsigned int port = m_conf.getDMRNetwork1Port(); @@ -918,8 +917,8 @@ bool CDMRGateway::createDMRNetwork1(bool trace) LogInfo(" Rewrite RF: %u:TG%u-TG%u -> %u:TG%u-TG%u", (*it).m_fromSlot, (*it).m_fromTG, (*it).m_fromTG + (*it).m_range - 1U, (*it).m_toSlot, (*it).m_toTG, (*it).m_toTG + (*it).m_range - 1U); LogInfo(" Rewrite Net: %u:TG%u-TG%u -> %u:TG%u-TG%u", (*it).m_toSlot, (*it).m_toTG, (*it).m_toTG + (*it).m_range - 1U, (*it).m_fromSlot, (*it).m_fromTG, (*it).m_fromTG + (*it).m_range - 1U); - CRewriteTG* rfRewrite = new CRewriteTG("DMR-1", (*it).m_fromSlot, (*it).m_fromTG, (*it).m_toSlot, (*it).m_toTG, (*it).m_range, trace); - CRewriteTG* netRewrite = new CRewriteTG("DMR-1", (*it).m_toSlot, (*it).m_toTG, (*it).m_fromSlot, (*it).m_fromTG, (*it).m_range, trace); + CRewriteTG* rfRewrite = new CRewriteTG("DMR-1", (*it).m_fromSlot, (*it).m_fromTG, (*it).m_toSlot, (*it).m_toTG, (*it).m_range); + CRewriteTG* netRewrite = new CRewriteTG("DMR-1", (*it).m_toSlot, (*it).m_toTG, (*it).m_fromSlot, (*it).m_fromTG, (*it).m_range); m_dmr1RFRewrites.push_back(rfRewrite); m_dmr1NetRewrites.push_back(netRewrite); @@ -929,7 +928,7 @@ bool CDMRGateway::createDMRNetwork1(bool trace) for (std::vector::const_iterator it = pcRewrites.begin(); it != pcRewrites.end(); ++it) { LogInfo(" Rewrite RF: %u:%u-%u -> %u:%u-%u", (*it).m_fromSlot, (*it).m_fromId, (*it).m_fromId + (*it).m_range - 1U, (*it).m_toSlot, (*it).m_toId, (*it).m_toId + (*it).m_range - 1U); - CRewritePC* rewrite = new CRewritePC("DMR-1", (*it).m_fromSlot, (*it).m_fromId, (*it).m_toSlot, (*it).m_toId, (*it).m_range, trace); + CRewritePC* rewrite = new CRewritePC("DMR-1", (*it).m_fromSlot, (*it).m_fromId, (*it).m_toSlot, (*it).m_toId, (*it).m_range); m_dmr1RFRewrites.push_back(rewrite); } @@ -938,7 +937,7 @@ bool CDMRGateway::createDMRNetwork1(bool trace) for (std::vector::const_iterator it = typeRewrites.begin(); it != typeRewrites.end(); ++it) { LogInfo(" Rewrite RF: %u:TG%u -> %u:%u", (*it).m_fromSlot, (*it).m_fromTG, (*it).m_toSlot, (*it).m_toId); - CRewriteType* rewrite = new CRewriteType("DMR-1", (*it).m_fromSlot, (*it).m_fromTG, (*it).m_toSlot, (*it).m_toId, trace); + CRewriteType* rewrite = new CRewriteType("DMR-1", (*it).m_fromSlot, (*it).m_fromTG, (*it).m_toSlot, (*it).m_toId); m_dmr1RFRewrites.push_back(rewrite); } @@ -947,7 +946,7 @@ bool CDMRGateway::createDMRNetwork1(bool trace) for (std::vector::const_iterator it = srcRewrites.begin(); it != srcRewrites.end(); ++it) { LogInfo(" Rewrite Net: %u:%u-%u -> %u:TG%u", (*it).m_fromSlot, (*it).m_fromId, (*it).m_fromId + (*it).m_range - 1U, (*it).m_toSlot, (*it).m_toTG); - CRewriteSrc* rewrite = new CRewriteSrc("DMR-1", (*it).m_fromSlot, (*it).m_fromId, (*it).m_toSlot, (*it).m_toTG, (*it).m_range, trace); + CRewriteSrc* rewrite = new CRewriteSrc("DMR-1", (*it).m_fromSlot, (*it).m_fromId, (*it).m_toSlot, (*it).m_toTG, (*it).m_range); m_dmr1NetRewrites.push_back(rewrite); } @@ -956,8 +955,8 @@ bool CDMRGateway::createDMRNetwork1(bool trace) for (std::vector::const_iterator it = tgPassAll.begin(); it != tgPassAll.end(); ++it) { LogInfo(" Pass All TG: %u", *it); - CPassAllTG* rfPassAllTG = new CPassAllTG("DMR-1", *it, trace); - CPassAllTG* netPassAllTG = new CPassAllTG("DMR-1", *it, trace); + CPassAllTG* rfPassAllTG = new CPassAllTG("DMR-1", *it); + CPassAllTG* netPassAllTG = new CPassAllTG("DMR-1", *it); m_dmr1Passalls.push_back(rfPassAllTG); m_dmr1NetRewrites.push_back(netPassAllTG); @@ -967,8 +966,8 @@ bool CDMRGateway::createDMRNetwork1(bool trace) for (std::vector::const_iterator it = pcPassAll.begin(); it != pcPassAll.end(); ++it) { LogInfo(" Pass All PC: %u", *it); - CPassAllPC* rfPassAllPC = new CPassAllPC("DMR-1", *it, trace); - CPassAllPC* netPassAllPC = new CPassAllPC("DMR-1", *it, trace); + CPassAllPC* rfPassAllPC = new CPassAllPC("DMR-1", *it); + CPassAllPC* netPassAllPC = new CPassAllPC("DMR-1", *it); m_dmr1Passalls.push_back(rfPassAllPC); m_dmr1NetRewrites.push_back(netPassAllPC); @@ -977,7 +976,7 @@ bool CDMRGateway::createDMRNetwork1(bool trace) return true; } -bool CDMRGateway::createDMRNetwork2(bool trace) +bool CDMRGateway::createDMRNetwork2() { std::string address = m_conf.getDMRNetwork2Address(); unsigned int port = m_conf.getDMRNetwork2Port(); @@ -1026,8 +1025,8 @@ bool CDMRGateway::createDMRNetwork2(bool trace) LogInfo(" Rewrite RF: %u:TG%u-TG%u -> %u:TG%u-TG%u", (*it).m_fromSlot, (*it).m_fromTG, (*it).m_fromTG + (*it).m_range - 1U, (*it).m_toSlot, (*it).m_toTG, (*it).m_toTG + (*it).m_range - 1U); LogInfo(" Rewrite Net: %u:TG%u-TG%u -> %u:TG%u-TG%u", (*it).m_toSlot, (*it).m_toTG, (*it).m_toTG + (*it).m_range - 1U, (*it).m_fromSlot, (*it).m_fromTG, (*it).m_fromTG + (*it).m_range - 1U); - CRewriteTG* rfRewrite = new CRewriteTG("DMR-2", (*it).m_fromSlot, (*it).m_fromTG, (*it).m_toSlot, (*it).m_toTG, (*it).m_range, trace); - CRewriteTG* netRewrite = new CRewriteTG("DMR-2", (*it).m_toSlot, (*it).m_toTG, (*it).m_fromSlot, (*it).m_fromTG, (*it).m_range, trace); + CRewriteTG* rfRewrite = new CRewriteTG("DMR-2", (*it).m_fromSlot, (*it).m_fromTG, (*it).m_toSlot, (*it).m_toTG, (*it).m_range); + CRewriteTG* netRewrite = new CRewriteTG("DMR-2", (*it).m_toSlot, (*it).m_toTG, (*it).m_fromSlot, (*it).m_fromTG, (*it).m_range); m_dmr2RFRewrites.push_back(rfRewrite); m_dmr2NetRewrites.push_back(netRewrite); @@ -1037,7 +1036,7 @@ bool CDMRGateway::createDMRNetwork2(bool trace) for (std::vector::const_iterator it = pcRewrites.begin(); it != pcRewrites.end(); ++it) { LogInfo(" Rewrite RF: %u:%u-%u -> %u:%u-%u", (*it).m_fromSlot, (*it).m_fromId, (*it).m_fromId + (*it).m_range - 1U, (*it).m_toSlot, (*it).m_toId, (*it).m_toId + (*it).m_range - 1U); - CRewritePC* rewrite = new CRewritePC("DMR-2", (*it).m_fromSlot, (*it).m_fromId, (*it).m_toSlot, (*it).m_toId, (*it).m_range, trace); + CRewritePC* rewrite = new CRewritePC("DMR-2", (*it).m_fromSlot, (*it).m_fromId, (*it).m_toSlot, (*it).m_toId, (*it).m_range); m_dmr2RFRewrites.push_back(rewrite); } @@ -1046,7 +1045,7 @@ bool CDMRGateway::createDMRNetwork2(bool trace) for (std::vector::const_iterator it = typeRewrites.begin(); it != typeRewrites.end(); ++it) { LogInfo(" Rewrite RF: %u:TG%u -> %u:%u", (*it).m_fromSlot, (*it).m_fromTG, (*it).m_toSlot, (*it).m_toId); - CRewriteType* rewrite = new CRewriteType("DMR-2", (*it).m_fromSlot, (*it).m_fromTG, (*it).m_toSlot, (*it).m_toId, trace); + CRewriteType* rewrite = new CRewriteType("DMR-2", (*it).m_fromSlot, (*it).m_fromTG, (*it).m_toSlot, (*it).m_toId); m_dmr2RFRewrites.push_back(rewrite); } @@ -1055,7 +1054,7 @@ bool CDMRGateway::createDMRNetwork2(bool trace) for (std::vector::const_iterator it = srcRewrites.begin(); it != srcRewrites.end(); ++it) { LogInfo(" Rewrite Net: %u:%u-%u -> %u:TG%u", (*it).m_fromSlot, (*it).m_fromId, (*it).m_fromId + (*it).m_range - 1U, (*it).m_toSlot, (*it).m_toTG); - CRewriteSrc* rewrite = new CRewriteSrc("DMR-2", (*it).m_fromSlot, (*it).m_fromId, (*it).m_toSlot, (*it).m_toTG, (*it).m_range, trace); + CRewriteSrc* rewrite = new CRewriteSrc("DMR-2", (*it).m_fromSlot, (*it).m_fromId, (*it).m_toSlot, (*it).m_toTG, (*it).m_range); m_dmr2NetRewrites.push_back(rewrite); } @@ -1064,8 +1063,8 @@ bool CDMRGateway::createDMRNetwork2(bool trace) for (std::vector::const_iterator it = tgPassAll.begin(); it != tgPassAll.end(); ++it) { LogInfo(" Pass All TG: %u", *it); - CPassAllTG* rfPassAllTG = new CPassAllTG("DMR-2", *it, trace); - CPassAllTG* netPassAllTG = new CPassAllTG("DMR-2", *it, trace); + CPassAllTG* rfPassAllTG = new CPassAllTG("DMR-2", *it); + CPassAllTG* netPassAllTG = new CPassAllTG("DMR-2", *it); m_dmr2Passalls.push_back(rfPassAllTG); m_dmr2NetRewrites.push_back(netPassAllTG); @@ -1075,8 +1074,8 @@ bool CDMRGateway::createDMRNetwork2(bool trace) for (std::vector::const_iterator it = pcPassAll.begin(); it != pcPassAll.end(); ++it) { LogInfo(" Pass All PC: %u", *it); - CPassAllPC* rfPassAllPC = new CPassAllPC("DMR-2", *it, trace); - CPassAllPC* netPassAllPC = new CPassAllPC("DMR-2", *it, trace); + CPassAllPC* rfPassAllPC = new CPassAllPC("DMR-2", *it); + CPassAllPC* netPassAllPC = new CPassAllPC("DMR-2", *it); m_dmr2Passalls.push_back(rfPassAllPC); m_dmr2NetRewrites.push_back(netPassAllPC); @@ -1137,8 +1136,8 @@ bool CDMRGateway::createXLXNetwork1() if (m_xlx1Startup != 4000U) LogInfo(" Startup: %u", m_xlx1Startup); - m_rpt1Rewrite = new CRewriteTG("XLX-1", XLX_SLOT, XLX_TG, m_xlx1Slot, m_xlx1TG, 1U, false); - m_xlx1Rewrite = new CRewriteTG("XLX-1", m_xlx1Slot, m_xlx1TG, XLX_SLOT, XLX_TG, 1U, false); + m_rpt1Rewrite = new CRewriteTG("XLX-1", XLX_SLOT, XLX_TG, m_xlx1Slot, m_xlx1TG, 1U); + m_xlx1Rewrite = new CRewriteTG("XLX-1", m_xlx1Slot, m_xlx1TG, XLX_SLOT, XLX_TG, 1U); return true; } @@ -1195,8 +1194,8 @@ bool CDMRGateway::createXLXNetwork2() if (m_xlx2Startup != 4000U) LogInfo(" Startup: %u", m_xlx2Startup); - m_rpt2Rewrite = new CRewriteTG("XLX-2", XLX_SLOT, XLX_TG, m_xlx2Slot, m_xlx2TG, 1U, false); - m_xlx2Rewrite = new CRewriteTG("XLX-2", m_xlx2Slot, m_xlx2TG, XLX_SLOT, XLX_TG, 1U, false); + m_rpt2Rewrite = new CRewriteTG("XLX-2", XLX_SLOT, XLX_TG, m_xlx2Slot, m_xlx2TG, 1U); + m_xlx2Rewrite = new CRewriteTG("XLX-2", m_xlx2Slot, m_xlx2TG, XLX_SLOT, XLX_TG, 1U); return true; } diff --git a/DMRGateway.h b/DMRGateway.h index fa35507..345ac5d 100644 --- a/DMRGateway.h +++ b/DMRGateway.h @@ -69,8 +69,8 @@ private: std::vector m_dmr2Passalls; bool createMMDVM(); - bool createDMRNetwork1(bool trace); - bool createDMRNetwork2(bool trace); + bool createDMRNetwork1(); + bool createDMRNetwork2(); bool createXLXNetwork1(); bool createXLXNetwork2(); void writeXLXLink(unsigned int srcId, unsigned int dstId, CDMRNetwork* network); diff --git a/PassAllPC.cpp b/PassAllPC.cpp index 8852efb..edf5f50 100644 --- a/PassAllPC.cpp +++ b/PassAllPC.cpp @@ -24,10 +24,9 @@ #include #include -CPassAllPC::CPassAllPC(const char* name, unsigned int slot, bool trace) : +CPassAllPC::CPassAllPC(const char* name, unsigned int slot) : m_name(name), -m_slot(slot), -m_trace(trace) +m_slot(slot) { assert(slot == 1U || slot == 2U); } @@ -36,30 +35,15 @@ CPassAllPC::~CPassAllPC() { } -bool CPassAllPC::processRF(CDMRData& data) -{ - bool ret = process(data); - - if (m_trace) - LogDebug("Rule Trace,\tPassAllPC %s Slot=%u: %s", m_name, m_slot, ret ? "matched" : "not matched"); - - return ret; -} - -bool CPassAllPC::processNet(CDMRData& data) -{ - bool ret = process(data); - - if (m_trace) - LogDebug("Rule Trace,\tPassAllPC %s Slot=%u: %s", m_name, m_slot, ret ? "matched" : "not matched"); - - return ret; -} - -bool CPassAllPC::process(CDMRData& data) +bool CPassAllPC::process(CDMRData& data, bool trace) { FLCO flco = data.getFLCO(); unsigned int slotNo = data.getSlotNo(); - return flco == FLCO_USER_USER && slotNo == m_slot; + bool ret = (flco == FLCO_USER_USER && slotNo == m_slot); + + if (trace) + LogDebug("Rule Trace,\tPassAllPC %s Slot=%u: %s", m_name, m_slot, ret ? "matched" : "not matched"); + + return ret; } diff --git a/PassAllPC.h b/PassAllPC.h index cee8729..108d981 100644 --- a/PassAllPC.h +++ b/PassAllPC.h @@ -24,18 +24,14 @@ class CPassAllPC : public IRewrite { public: - CPassAllPC(const char* name, unsigned int slot, bool trace); + CPassAllPC(const char* name, unsigned int slot); virtual ~CPassAllPC(); - virtual bool processRF(CDMRData& data); - virtual bool processNet(CDMRData& data); + virtual bool process(CDMRData& data, bool trace); private: const char* m_name; unsigned int m_slot; - bool m_trace; - - bool process(CDMRData& data); }; diff --git a/PassAllTG.cpp b/PassAllTG.cpp index a11697d..90f7ce5 100644 --- a/PassAllTG.cpp +++ b/PassAllTG.cpp @@ -24,10 +24,9 @@ #include #include -CPassAllTG::CPassAllTG(const char* name, unsigned int slot, bool trace) : +CPassAllTG::CPassAllTG(const char* name, unsigned int slot) : m_name(name), -m_slot(slot), -m_trace(trace) +m_slot(slot) { assert(slot == 1U || slot == 2U); } @@ -36,30 +35,15 @@ CPassAllTG::~CPassAllTG() { } -bool CPassAllTG::processRF(CDMRData& data) -{ - bool ret = process(data); - - if (m_trace) - LogDebug("Rule Trace,\tPassAllTG %s Slot=%u: %s", m_name, m_slot, ret ? "matched" : "not matched"); - - return ret; -} - -bool CPassAllTG::processNet(CDMRData& data) -{ - bool ret = process(data); - - if (m_trace) - LogDebug("Rule Trace,\tPassAllTG %s Slot=%u: %s", m_name, m_slot, ret ? "matched" : "not matched"); - - return ret; -} - -bool CPassAllTG::process(CDMRData& data) +bool CPassAllTG::process(CDMRData& data, bool trace) { FLCO flco = data.getFLCO(); unsigned int slotNo = data.getSlotNo(); - return flco == FLCO_GROUP && slotNo == m_slot; + bool ret = (flco == FLCO_GROUP && slotNo == m_slot); + + if (trace) + LogDebug("Rule Trace,\tPassAllTG %s Slot=%u: %s", m_name, m_slot, ret ? "matched" : "not matched"); + + return ret; } diff --git a/PassAllTG.h b/PassAllTG.h index 9780d61..032eec4 100644 --- a/PassAllTG.h +++ b/PassAllTG.h @@ -24,18 +24,14 @@ class CPassAllTG : public IRewrite { public: - CPassAllTG(const char* name, unsigned int slot, bool trace); + CPassAllTG(const char* name, unsigned int slot); virtual ~CPassAllTG(); - virtual bool processRF(CDMRData& data); - virtual bool processNet(CDMRData& data); + virtual bool process(CDMRData& data, bool trace); private: const char* m_name; unsigned int m_slot; - bool m_trace; - - bool process(CDMRData& data); }; diff --git a/Rewrite.h b/Rewrite.h index c33723c..0292d10 100644 --- a/Rewrite.h +++ b/Rewrite.h @@ -25,8 +25,7 @@ class IRewrite { public: virtual ~IRewrite() = 0; - virtual bool processRF(CDMRData& data) = 0; - virtual bool processNet(CDMRData& data) = 0; + virtual bool process(CDMRData& data, bool trace) = 0; private: }; diff --git a/RewritePC.cpp b/RewritePC.cpp index 2f76aea..55c1367 100644 --- a/RewritePC.cpp +++ b/RewritePC.cpp @@ -25,7 +25,7 @@ #include #include -CRewritePC::CRewritePC(const char* name, unsigned int fromSlot, unsigned int fromId, unsigned int toSlot, unsigned int toId, unsigned int range, bool trace) : +CRewritePC::CRewritePC(const char* name, unsigned int fromSlot, unsigned int fromId, unsigned int toSlot, unsigned int toId, unsigned int range) : m_name(name), m_fromSlot(fromSlot), m_fromIdStart(fromId), @@ -33,7 +33,6 @@ m_fromIdEnd(fromId + range - 1U), m_toSlot(toSlot), m_toIdStart(toId), m_toIdEnd(toId + range - 1U), -m_trace(trace), m_lc(FLCO_USER_USER, 0U, 0U), m_embeddedLC() { @@ -45,40 +44,17 @@ CRewritePC::~CRewritePC() { } -bool CRewritePC::processRF(CDMRData& data) -{ - bool ret = process(data); - - if (m_trace) - LogDebug("Rule Trace,\tRewritePC from %s Slot=%u Dst=%u-%u: %s", m_name, m_fromSlot, m_fromIdStart, m_fromIdEnd, ret ? "matched" : "not matched"); - - if (m_trace && ret) - LogDebug("Rule Trace,\tRewritePC to %s Slot=%u Dst=%u-%u", m_name, m_toSlot, m_toIdStart, m_toIdEnd); - - return ret; -} - -bool CRewritePC::processNet(CDMRData& data) -{ - bool ret = process(data); - - if (m_trace) - LogDebug("Rule Trace,\tRewritePC from %s Slot=%u Dst=%u-%u: %s", m_name, m_fromSlot, m_fromIdStart, m_fromIdEnd, ret ? "matched" : "not matched"); - - if (m_trace && ret) - LogDebug("Rule Trace,\tRewritePC to %s Slot=%u Dst=%u-%u", m_name, m_toSlot, m_toIdStart, m_toIdEnd); - - return ret; -} - -bool CRewritePC::process(CDMRData& data) +bool CRewritePC::process(CDMRData& data, bool trace) { FLCO flco = data.getFLCO(); unsigned int dstId = data.getDstId(); unsigned int slotNo = data.getSlotNo(); - if (flco != FLCO_USER_USER || slotNo != m_fromSlot || dstId < m_fromIdStart || dstId > m_fromIdEnd) + if (flco != FLCO_USER_USER || slotNo != m_fromSlot || dstId < m_fromIdStart || dstId > m_fromIdEnd) { + if (trace) + LogDebug("Rule Trace,\tRewritePC from %s Slot=%u Dst=%u-%u: not matched", m_name, m_fromSlot, m_fromIdStart, m_fromIdEnd); return false; + } if (m_fromSlot != m_toSlot) data.setSlotNo(m_toSlot); @@ -107,6 +83,11 @@ bool CRewritePC::process(CDMRData& data) } } + if (trace) { + LogDebug("Rule Trace,\tRewritePC from %s Slot=%u Dst=%u-%u: not matched", m_name, m_fromSlot, m_fromIdStart, m_fromIdEnd); + LogDebug("Rule Trace,\tRewritePC to %s Slot=%u Dst=%u-%u", m_name, m_toSlot, m_toIdStart, m_toIdEnd); + } + return true; } diff --git a/RewritePC.h b/RewritePC.h index 0379a12..9486a90 100644 --- a/RewritePC.h +++ b/RewritePC.h @@ -26,11 +26,10 @@ class CRewritePC : public IRewrite { public: - CRewritePC(const char* name, unsigned int fromSlot, unsigned int fromId, unsigned int toSlot, unsigned int toId, unsigned int range, bool trace); + CRewritePC(const char* name, unsigned int fromSlot, unsigned int fromId, unsigned int toSlot, unsigned int toId, unsigned int range); virtual ~CRewritePC(); - virtual bool processRF(CDMRData& data); - virtual bool processNet(CDMRData& data); + virtual bool process(CDMRData& data, bool trace); private: const char* m_name; @@ -40,11 +39,9 @@ private: unsigned int m_toSlot; unsigned int m_toIdStart; unsigned int m_toIdEnd; - bool m_trace; CDMRLC m_lc; CDMREmbeddedData m_embeddedLC; - bool process(CDMRData& data); void processHeader(CDMRData& data, unsigned int dstId, unsigned char dataType); void processVoice(CDMRData& data, unsigned int dstId); }; diff --git a/RewriteSrc.cpp b/RewriteSrc.cpp index e9c8f3e..1b3e890 100644 --- a/RewriteSrc.cpp +++ b/RewriteSrc.cpp @@ -25,14 +25,13 @@ #include #include -CRewriteSrc::CRewriteSrc(const char* name, unsigned int fromSlot, unsigned int fromId, unsigned int toSlot, unsigned int toTG, unsigned int range, bool trace) : +CRewriteSrc::CRewriteSrc(const char* name, unsigned int fromSlot, unsigned int fromId, unsigned int toSlot, unsigned int toTG, unsigned int range) : m_name(name), m_fromSlot(fromSlot), m_fromIdStart(fromId), m_fromIdEnd(fromId + range - 1U), m_toSlot(toSlot), m_toTG(toTG), -m_trace(trace), m_lc(FLCO_GROUP, 0U, toTG), m_embeddedLC() { @@ -46,40 +45,17 @@ CRewriteSrc::~CRewriteSrc() { } -bool CRewriteSrc::processRF(CDMRData& data) -{ - bool ret = process(data); - - if (m_trace) - LogDebug("Rule Trace,\tRewriteSrc from %s Slot=%u Src=%u-%u: %s", m_name, m_fromSlot, m_fromIdStart, m_fromIdEnd, ret ? "matched" : "not matched"); - - if (m_trace && ret) - LogDebug("Rule Trace,\tRewriteSrc to %s Slot=%u Dst=TG%u", m_name, m_toSlot, m_toTG); - - return ret; -} - -bool CRewriteSrc::processNet(CDMRData& data) -{ - bool ret = process(data); - - if (m_trace) - LogDebug("Rule Trace,\tRewriteSrc from %s Slot=%u Src=%u-%u: %s", m_name, m_fromSlot, m_fromIdStart, m_fromIdEnd, ret ? "matched" : "not matched"); - - if (m_trace && ret) - LogDebug("Rule Trace,\tRewriteSrc to %s Slot=%u Dst=TG%u", m_name, m_toSlot, m_toTG); - - return ret; -} - -bool CRewriteSrc::process(CDMRData& data) +bool CRewriteSrc::process(CDMRData& data, bool trace) { FLCO flco = data.getFLCO(); unsigned int srcId = data.getSrcId(); unsigned int slotNo = data.getSlotNo(); - if (flco != FLCO_USER_USER || slotNo != m_fromSlot || srcId < m_fromIdStart || srcId > m_fromIdEnd) + if (flco != FLCO_USER_USER || slotNo != m_fromSlot || srcId < m_fromIdStart || srcId > m_fromIdEnd) { + if (trace) + LogDebug("Rule Trace,\tRewriteSrc from %s Slot=%u Src=%u-%u: not matched", m_name, m_fromSlot, m_fromIdStart, m_fromIdEnd); return false; + } if (m_fromSlot != m_toSlot) data.setSlotNo(m_toSlot); @@ -105,6 +81,11 @@ bool CRewriteSrc::process(CDMRData& data) break; } + if (trace) { + LogDebug("Rule Trace,\tRewriteSrc from %s Slot=%u Src=%u-%u: matched", m_name, m_fromSlot, m_fromIdStart, m_fromIdEnd); + LogDebug("Rule Trace,\tRewriteSrc to %s Slot=%u Dst=TG%u", m_name, m_toSlot, m_toTG); + } + return true; } diff --git a/RewriteSrc.h b/RewriteSrc.h index 3bc2325..ff323bb 100644 --- a/RewriteSrc.h +++ b/RewriteSrc.h @@ -26,11 +26,10 @@ class CRewriteSrc : public IRewrite { public: - CRewriteSrc(const char* name, unsigned int fromSlot, unsigned int fromId, unsigned int toSlot, unsigned int toTG, unsigned int range, bool trace); + CRewriteSrc(const char* name, unsigned int fromSlot, unsigned int fromId, unsigned int toSlot, unsigned int toTG, unsigned int range); virtual ~CRewriteSrc(); - virtual bool processRF(CDMRData& data); - virtual bool processNet(CDMRData& data); + virtual bool process(CDMRData& data, bool trace); private: const char* m_name; @@ -39,11 +38,9 @@ private: unsigned int m_fromIdEnd; unsigned int m_toSlot; unsigned int m_toTG; - bool m_trace; CDMRLC m_lc; CDMREmbeddedData m_embeddedLC; - bool process(CDMRData& data); void processHeader(CDMRData& data, unsigned char dataType); void processVoice(CDMRData& data); }; diff --git a/RewriteTG.cpp b/RewriteTG.cpp index 63e3693..0ce9be4 100644 --- a/RewriteTG.cpp +++ b/RewriteTG.cpp @@ -25,7 +25,7 @@ #include #include -CRewriteTG::CRewriteTG(const char* name, unsigned int fromSlot, unsigned int fromTG, unsigned int toSlot, unsigned int toTG, unsigned int range, bool trace) : +CRewriteTG::CRewriteTG(const char* name, unsigned int fromSlot, unsigned int fromTG, unsigned int toSlot, unsigned int toTG, unsigned int range) : m_name(name), m_fromSlot(fromSlot), m_fromTGStart(fromTG), @@ -33,7 +33,6 @@ m_fromTGEnd(fromTG + range - 1U), m_toSlot(toSlot), m_toTGStart(toTG), m_toTGEnd(toTG + range - 1U), -m_trace(trace), m_lc(FLCO_GROUP, 0U, toTG), m_embeddedLC() { @@ -45,40 +44,17 @@ CRewriteTG::~CRewriteTG() { } -bool CRewriteTG::processRF(CDMRData& data) +bool CRewriteTG::process(CDMRData& data, bool trace) { - bool ret = process(data); - - if (m_trace) - LogDebug("Rule Trace,\tRewriteTG from %s Slot=%u Dst=TG%u-TG%u: %s", m_name, m_fromSlot, m_fromTGStart, m_fromTGEnd, ret ? "matched" : "not matched"); - - if (m_trace && ret) - LogDebug("Rule Trace,\tRewriteTG to %s Slot=%u Dst=TG%u-TG%u", m_name, m_toSlot, m_toTGStart, m_toTGEnd); - - return ret; -} - -bool CRewriteTG::processNet(CDMRData& data) -{ - bool ret = process(data); - - if (m_trace) - LogDebug("Rule Trace,\tRewriteTG from %s Slot=%u Dst=TG%u-TG%u: %s", m_name, m_fromSlot, m_fromTGStart, m_fromTGEnd, ret ? "matched" : "not matched"); - - if (m_trace && ret) - LogDebug("Rule Trace,\tRewriteTG to %s Slot=%u Dst=TG%u-TG%u", m_name, m_toSlot, m_toTGStart, m_toTGEnd); - - return ret; -} - -bool CRewriteTG::process(CDMRData& data) -{ - FLCO flco = data.getFLCO(); - unsigned int dstId = data.getDstId(); + FLCO flco = data.getFLCO(); + unsigned int dstId = data.getDstId(); unsigned int slotNo = data.getSlotNo(); - if (flco != FLCO_GROUP || slotNo != m_fromSlot || dstId < m_fromTGStart || dstId > m_fromTGEnd) + if (flco != FLCO_GROUP || slotNo != m_fromSlot || dstId < m_fromTGStart || dstId > m_fromTGEnd) { + if (trace) + LogDebug("Rule Trace,\tRewriteTG from %s Slot=%u Dst=TG%u-TG%u: not matched", m_name, m_fromSlot, m_fromTGStart, m_fromTGEnd); return false; + } if (m_fromSlot != m_toSlot) data.setSlotNo(m_toSlot); @@ -107,6 +83,11 @@ bool CRewriteTG::process(CDMRData& data) } } + if (trace) { + LogDebug("Rule Trace,\tRewriteTG from %s Slot=%u Dst=TG%u-TG%u: matched", m_name, m_fromSlot, m_fromTGStart, m_fromTGEnd); + LogDebug("Rule Trace,\tRewriteTG to %s Slot=%u Dst=TG%u-TG%u", m_name, m_toSlot, m_toTGStart, m_toTGEnd); + } + return true; } diff --git a/RewriteTG.h b/RewriteTG.h index 3db2266..26d2f7d 100644 --- a/RewriteTG.h +++ b/RewriteTG.h @@ -26,11 +26,10 @@ class CRewriteTG : public IRewrite { public: - CRewriteTG(const char*name, unsigned int fromSlot, unsigned int fromTG, unsigned int toSlot, unsigned int toTG, unsigned int range, bool trace); + CRewriteTG(const char*name, unsigned int fromSlot, unsigned int fromTG, unsigned int toSlot, unsigned int toTG, unsigned int range); virtual ~CRewriteTG(); - virtual bool processRF(CDMRData& data); - virtual bool processNet(CDMRData& data); + virtual bool process(CDMRData& data, bool trace); private: const char* m_name; @@ -40,11 +39,9 @@ private: unsigned int m_toSlot; unsigned int m_toTGStart; unsigned int m_toTGEnd; - bool m_trace; CDMRLC m_lc; CDMREmbeddedData m_embeddedLC; - bool process(CDMRData& data); void processHeader(CDMRData& data, unsigned int tg, unsigned char dataType); void processVoice(CDMRData& data, unsigned int tg); }; diff --git a/RewriteType.cpp b/RewriteType.cpp index 6f277cf..a4c0b39 100644 --- a/RewriteType.cpp +++ b/RewriteType.cpp @@ -25,13 +25,12 @@ #include #include -CRewriteType::CRewriteType(const char* name, unsigned int fromSlot, unsigned int fromTG, unsigned int toSlot, unsigned int toId, bool trace) : +CRewriteType::CRewriteType(const char* name, unsigned int fromSlot, unsigned int fromTG, unsigned int toSlot, unsigned int toId) : m_name(name), m_fromSlot(fromSlot), m_fromTG(fromTG), m_toSlot(toSlot), m_toId(toId), -m_trace(trace), m_lc(FLCO_USER_USER, 0U, toId), m_embeddedLC() { @@ -43,34 +42,17 @@ CRewriteType::~CRewriteType() { } -bool CRewriteType::processRF(CDMRData& data) -{ - bool ret = process(data); - - if (m_trace) - LogDebug("Rule Trace,\tRewriteType %s Slot=%u Dst=TG%u: %s", m_name, m_fromSlot, m_fromTG, ret ? "matched" : "not matched"); - - return ret; -} - -bool CRewriteType::processNet(CDMRData& data) -{ - bool ret = process(data); - - if (m_trace) - LogDebug("Rule Trace,\tRewriteType %s Slot=%u Dst=TG%u: %s", m_name, m_fromSlot, m_fromTG, ret ? "matched" : "not matched"); - - return ret; -} - -bool CRewriteType::process(CDMRData& data) +bool CRewriteType::process(CDMRData& data, bool trace) { FLCO flco = data.getFLCO(); unsigned int dstId = data.getDstId(); unsigned int slotNo = data.getSlotNo(); - if (flco != FLCO_GROUP || slotNo != m_fromSlot || dstId != m_fromTG) + if (flco != FLCO_GROUP || slotNo != m_fromSlot || dstId != m_fromTG) { + if (trace) + LogDebug("Rule Trace,\tRewriteType %s Slot=%u Dst=TG%u: not matched", m_name, m_fromSlot, m_fromTG); return false; + } if (m_fromSlot != m_toSlot) data.setSlotNo(m_toSlot); @@ -96,6 +78,9 @@ bool CRewriteType::process(CDMRData& data) break; } + if (trace) + LogDebug("Rule Trace,\tRewriteType %s Slot=%u Dst=TG%u: matched", m_name, m_fromSlot, m_fromTG); + return true; } diff --git a/RewriteType.h b/RewriteType.h index ccac537..30e4d53 100644 --- a/RewriteType.h +++ b/RewriteType.h @@ -26,11 +26,10 @@ class CRewriteType : public IRewrite { public: - CRewriteType(const char* name, unsigned int fromSlot, unsigned int fromTG, unsigned int toSlot, unsigned int toId, bool trace); + CRewriteType(const char* name, unsigned int fromSlot, unsigned int fromTG, unsigned int toSlot, unsigned int toId); virtual ~CRewriteType(); - virtual bool processRF(CDMRData& data); - virtual bool processNet(CDMRData& data); + virtual bool process(CDMRData& data, bool trace); private: const char* m_name; @@ -38,11 +37,9 @@ private: unsigned int m_fromTG; unsigned int m_toSlot; unsigned int m_toId; - bool m_trace; CDMRLC m_lc; CDMREmbeddedData m_embeddedLC; - bool process(CDMRData& data); void processHeader(CDMRData& data, unsigned char dataType); void processVoice(CDMRData& data); }; From 4c64d3a8f74dd41d9f6048994db3b9f9149e0f99 Mon Sep 17 00:00:00 2001 From: g0wfv Date: Thu, 8 Jun 2017 09:43:30 +0100 Subject: [PATCH 16/20] Send MSTCL instead of MSTNAK --- MMDVMNetwork.cpp | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/MMDVMNetwork.cpp b/MMDVMNetwork.cpp index fc360a6..a09d5bb 100644 --- a/MMDVMNetwork.cpp +++ b/MMDVMNetwork.cpp @@ -260,12 +260,8 @@ void CMMDVMNetwork::close() LogMessage("DMR, Closing MMDVM Network"); - buffer[0U] = 'M'; - buffer[1U] = 'S'; - buffer[2U] = 'T'; - buffer[3U] = 'N'; - buffer[4U] = 'A'; - buffer[5U] = 'K'; + ::memcpy(buffer + 0U, "MSTCL", 5U); + ::memcpy(buffer + 5U, m_netId, 4U); m_socket.write(buffer, HOMEBREW_DATA_PACKET_LENGTH, m_rptAddress, m_rptPort); m_socket.close(); From 706d30303e67e324658a0680718ea725c7a529ad Mon Sep 17 00:00:00 2001 From: Tony Corbett G0WFV Date: Thu, 8 Jun 2017 10:15:00 +0100 Subject: [PATCH 17/20] Respond to MMDVM closing down --- MMDVMNetwork.cpp | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/MMDVMNetwork.cpp b/MMDVMNetwork.cpp index a09d5bb..7cbdb64 100644 --- a/MMDVMNetwork.cpp +++ b/MMDVMNetwork.cpp @@ -265,7 +265,6 @@ void CMMDVMNetwork::close() m_socket.write(buffer, HOMEBREW_DATA_PACKET_LENGTH, m_rptAddress, m_rptPort); m_socket.close(); - } void CMMDVMNetwork::clock(unsigned int ms) @@ -313,6 +312,8 @@ void CMMDVMNetwork::clock(unsigned int ms) ::memcpy(ack + 0U, "RPTACK", 6U); ::memcpy(ack + 6U, m_netId, 4U); m_socket.write(ack, 10U, m_rptAddress, m_rptPort); + } else if (::memcmp(m_buffer, "RPTCL", 5U) == 0) { + ::LogMessage("DMR, MMDVM is restarting"); } else if (::memcmp(m_buffer, "RPTC", 4U) == 0) { m_configLen = length - 8U; m_configData = new unsigned char[m_configLen]; From 2c94d8a6c2efe7d98849c2db1316131baa4ba32a Mon Sep 17 00:00:00 2001 From: g0wfv Date: Thu, 8 Jun 2017 10:29:36 +0100 Subject: [PATCH 18/20] Alter log messages to differentiate between DMR and MMDVM networks --- MMDVMNetwork.cpp | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/MMDVMNetwork.cpp b/MMDVMNetwork.cpp index 7cbdb64..11af70b 100644 --- a/MMDVMNetwork.cpp +++ b/MMDVMNetwork.cpp @@ -94,7 +94,7 @@ unsigned int CMMDVMNetwork::getId() const bool CMMDVMNetwork::open() { - LogMessage("DMR, Opening MMDVM Network"); + LogMessage("MMDVM Network, Opening"); return m_socket.open(); } @@ -258,7 +258,7 @@ void CMMDVMNetwork::close() unsigned char buffer[HOMEBREW_DATA_PACKET_LENGTH]; ::memset(buffer, 0x00U, HOMEBREW_DATA_PACKET_LENGTH); - LogMessage("DMR, Closing MMDVM Network"); + LogMessage("MMDVM Network, Closing"); ::memcpy(buffer + 0U, "MSTCL", 5U); ::memcpy(buffer + 5U, m_netId, 4U); @@ -273,7 +273,7 @@ void CMMDVMNetwork::clock(unsigned int ms) unsigned int port; int length = m_socket.read(m_buffer, BUFFER_LENGTH, address, port); if (length < 0) { - LogError("DMR, Socket has failed, reopening"); + LogError("MMDVM Network, Socket has failed, reopening"); close(); open(); return; @@ -313,7 +313,7 @@ void CMMDVMNetwork::clock(unsigned int ms) ::memcpy(ack + 6U, m_netId, 4U); m_socket.write(ack, 10U, m_rptAddress, m_rptPort); } else if (::memcmp(m_buffer, "RPTCL", 5U) == 0) { - ::LogMessage("DMR, MMDVM is restarting"); + ::LogMessage("MMDVM Network, The connected MMDVM is closing down"); } else if (::memcmp(m_buffer, "RPTC", 4U) == 0) { m_configLen = length - 8U; m_configData = new unsigned char[m_configLen]; From fc4d79abe902623de8b3b1444298858b89a726b6 Mon Sep 17 00:00:00 2001 From: g0wfv Date: Thu, 8 Jun 2017 10:31:08 +0100 Subject: [PATCH 19/20] Alter MSTNAK responses to differentiate stages of retry --- DMRNetwork.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/DMRNetwork.cpp b/DMRNetwork.cpp index 422b77a..888b499 100644 --- a/DMRNetwork.cpp +++ b/DMRNetwork.cpp @@ -324,7 +324,7 @@ void CDMRNetwork::clock(unsigned int ms) m_rxData.addData(m_buffer, len); } else if (::memcmp(m_buffer, "MSTNAK", 6U) == 0) { if (m_status == RUNNING) { - LogWarning("%s, The master is restarting, logging back in", m_name); + LogWarning("%s, Login to the master has failed, retrying login ...", m_name); m_status = WAITING_LOGIN; m_timeoutTimer.start(); m_retryTimer.start(); @@ -332,7 +332,7 @@ void CDMRNetwork::clock(unsigned int ms) /* Once the modem death spiral has been prevented in Modem.cpp the Network sometimes times out and reaches here. We want it to reconnect so... */ - LogError("%s, Login to the master has failed, retrying ...", m_name); + LogError("%s, Login to the master has failed, retrying network ...", m_name); close(); open(); return; From 048abc0888d2a6ef2dc2cb6afbc769c24b01ecbb Mon Sep 17 00:00:00 2001 From: Jonathan Naylor Date: Fri, 9 Jun 2017 20:14:26 +0100 Subject: [PATCH 20/20] Optimise the tracing to remove duplicate traces. --- DMRGateway.cpp | 57 +++++++++++++++++++++++++++++++++++++++----------- 1 file changed, 45 insertions(+), 12 deletions(-) diff --git a/DMRGateway.cpp b/DMRGateway.cpp index 9c16180..690b0fd 100644 --- a/DMRGateway.cpp +++ b/DMRGateway.cpp @@ -364,6 +364,18 @@ int CDMRGateway::run() status[1U] = DMRGWS_NONE; status[2U] = DMRGWS_NONE; + unsigned int rfSrcId[3U]; + unsigned int rfDstId[3U]; + rfSrcId[1U] = rfSrcId[2U] = rfDstId[1U] = rfDstId[2U] = 0U; + + unsigned int dmr1SrcId[3U]; + unsigned int dmr1DstId[3U]; + dmr1SrcId[1U] = dmr1SrcId[2U] = dmr1DstId[1U] = dmr1DstId[2U] = 0U; + + unsigned int dmr2SrcId[3U]; + unsigned int dmr2DstId[3U]; + dmr2SrcId[1U] = dmr2SrcId[2U] = dmr2DstId[1U] = dmr2DstId[2U] = 0U; + CStopWatch stopWatch; stopWatch.start(); @@ -527,7 +539,14 @@ int CDMRGateway::run() unsigned int dstId = data.getDstId(); FLCO flco = data.getFLCO(); - if (ruleTrace) + bool trace = false; + if (ruleTrace && (srcId != rfSrcId[slotNo] || dstId != rfDstId[slotNo])) { + rfSrcId[slotNo] = srcId; + rfDstId[slotNo] = dstId; + trace = true; + } + + if (trace) LogDebug("Rule Trace, RF transmission: Slot=%u Src=%u Dst=%s%u", slotNo, srcId, flco == FLCO_GROUP ? "TG" : "", dstId); bool rewritten = false; @@ -535,7 +554,7 @@ int CDMRGateway::run() if (m_dmrNetwork1 != NULL) { // Rewrite the slot and/or TG or neither for (std::vector::iterator it = m_dmr1RFRewrites.begin(); it != m_dmr1RFRewrites.end(); ++it) { - bool ret = (*it)->process(data, ruleTrace); + bool ret = (*it)->process(data, trace); if (ret) { rewritten = true; break; @@ -555,7 +574,7 @@ int CDMRGateway::run() if (m_dmrNetwork2 != NULL) { // Rewrite the slot and/or TG or neither for (std::vector::iterator it = m_dmr2RFRewrites.begin(); it != m_dmr2RFRewrites.end(); ++it) { - bool ret = (*it)->process(data, ruleTrace); + bool ret = (*it)->process(data, trace); if (ret) { rewritten = true; break; @@ -575,7 +594,7 @@ int CDMRGateway::run() if (!rewritten) { if (m_dmrNetwork1 != NULL) { for (std::vector::iterator it = m_dmr1Passalls.begin(); it != m_dmr1Passalls.end(); ++it) { - bool ret = (*it)->process(data, ruleTrace); + bool ret = (*it)->process(data, trace); if (ret) { rewritten = true; break; @@ -595,7 +614,7 @@ int CDMRGateway::run() if (!rewritten) { if (m_dmrNetwork2 != NULL) { for (std::vector::iterator it = m_dmr2Passalls.begin(); it != m_dmr2Passalls.end(); ++it) { - bool ret = (*it)->process(data, ruleTrace); + bool ret = (*it)->process(data, trace); if (ret) { rewritten = true; break; @@ -612,7 +631,7 @@ int CDMRGateway::run() } } - if (!rewritten && ruleTrace) + if (!rewritten && trace) LogDebug("Rule Trace,\tnot matched so rejected"); } } @@ -664,13 +683,20 @@ int CDMRGateway::run() unsigned int dstId = data.getDstId(); FLCO flco = data.getFLCO(); - if (ruleTrace) + bool trace = false; + if (ruleTrace && (srcId != dmr1SrcId[slotNo] || dstId != dmr1DstId[slotNo])) { + dmr1SrcId[slotNo] = srcId; + dmr1DstId[slotNo] = dstId; + trace = true; + } + + if (trace) LogDebug("Rule Trace, network 1 transmission: Slot=%u Src=%u Dst=%s%u", slotNo, srcId, flco == FLCO_GROUP ? "TG" : "", dstId); // Rewrite the slot and/or TG or neither bool rewritten = false; for (std::vector::iterator it = m_dmr1NetRewrites.begin(); it != m_dmr1NetRewrites.end(); ++it) { - bool ret = (*it)->process(data, ruleTrace); + bool ret = (*it)->process(data, trace); if (ret) { rewritten = true; break; @@ -685,7 +711,7 @@ int CDMRGateway::run() } } - if (!rewritten && ruleTrace) + if (!rewritten && trace) LogDebug("Rule Trace,\tnot matched so rejected"); } @@ -702,13 +728,20 @@ int CDMRGateway::run() unsigned int dstId = data.getDstId(); FLCO flco = data.getFLCO(); - if (ruleTrace) + bool trace = false; + if (ruleTrace && (srcId != dmr2SrcId[slotNo] || dstId != dmr2DstId[slotNo])) { + dmr2SrcId[slotNo] = srcId; + dmr2DstId[slotNo] = dstId; + trace = true; + } + + if (trace) LogDebug("Rule Trace, network 2 transmission: Slot=%u Src=%u Dst=%s%u", slotNo, srcId, flco == FLCO_GROUP ? "TG" : "", dstId); // Rewrite the slot and/or TG or neither bool rewritten = false; for (std::vector::iterator it = m_dmr2NetRewrites.begin(); it != m_dmr2NetRewrites.end(); ++it) { - bool ret = (*it)->process(data, ruleTrace); + bool ret = (*it)->process(data, trace); if (ret) { rewritten = true; break; @@ -723,7 +756,7 @@ int CDMRGateway::run() } } - if (!rewritten && ruleTrace) + if (!rewritten && trace) LogDebug("Rule Trace,\tnot matched so rejected"); }