mirror of
https://github.com/g4klx/DMRGateway
synced 2025-12-23 23:05:38 +08:00
Use the unified rewriting code.
This commit is contained in:
Jonathan Naylor
197
DMRGateway.cpp
197
DMRGateway.cpp
@@ -19,6 +19,7 @@
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#include "DMRGateway.h"
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#include "Version.h"
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#include "StopWatch.h"
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#include "RewritePC.h"
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#include "Thread.h"
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#include "Voice.h"
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#include "Log.h"
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@@ -126,27 +127,26 @@ m_xlxRewrite(NULL),
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m_dmr1NetRewrites(),
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m_dmr1RFRewrites(),
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m_dmr2NetRewrites(),
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m_dmr2RFRewrites(),
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m_dmr1PrivateSlot1(false),
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m_dmr1PrivateSlot2(false),
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m_dmr2PrivateSlot1(false),
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m_dmr2PrivateSlot2(false)
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m_dmr2RFRewrites()
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{
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}
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CDMRGateway::~CDMRGateway()
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{
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for (std::vector<CRewriteTG*>::iterator it = m_dmr1NetRewrites.begin(); it != m_dmr1NetRewrites.end(); ++it)
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for (std::vector<IRewrite*>::iterator it = m_dmr1NetRewrites.begin(); it != m_dmr1NetRewrites.end(); ++it)
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delete *it;
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for (std::vector<CRewriteTG*>::iterator it = m_dmr1RFRewrites.begin(); it != m_dmr1RFRewrites.end(); ++it)
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for (std::vector<IRewrite*>::iterator it = m_dmr1RFRewrites.begin(); it != m_dmr1RFRewrites.end(); ++it)
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delete *it;
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for (std::vector<CRewriteTG*>::iterator it = m_dmr2NetRewrites.begin(); it != m_dmr2NetRewrites.end(); ++it)
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for (std::vector<IRewrite*>::iterator it = m_dmr2NetRewrites.begin(); it != m_dmr2NetRewrites.end(); ++it)
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delete *it;
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for (std::vector<CRewriteTG*>::iterator it = m_dmr2RFRewrites.begin(); it != m_dmr2RFRewrites.end(); ++it)
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for (std::vector<IRewrite*>::iterator it = m_dmr2RFRewrites.begin(); it != m_dmr2RFRewrites.end(); ++it)
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delete *it;
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delete m_rptRewrite;
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delete m_xlxRewrite;
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}
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int CDMRGateway::run()
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@@ -346,30 +346,12 @@ int CDMRGateway::run()
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}
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}
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}
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} else if (flco == FLCO_USER_USER) {
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if (m_dmrNetwork1 != NULL && slotNo == 1U && m_dmr1PrivateSlot1) {
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m_dmrNetwork1->write(data);
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status[slotNo] = DMRGWS_NETWORK1;
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timer[slotNo]->start();
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} else if (m_dmrNetwork1 != NULL && slotNo == 2U && m_dmr1PrivateSlot2) {
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m_dmrNetwork1->write(data);
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status[slotNo] = DMRGWS_NETWORK1;
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timer[slotNo]->start();
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} else if (m_dmrNetwork2 != NULL && slotNo == 1U && m_dmr2PrivateSlot1) {
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m_dmrNetwork2->write(data);
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status[slotNo] = DMRGWS_NETWORK2;
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timer[slotNo]->start();
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} else if (m_dmrNetwork2 != NULL && slotNo == 2U && m_dmr2PrivateSlot2) {
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m_dmrNetwork2->write(data);
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status[slotNo] = DMRGWS_NETWORK2;
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timer[slotNo]->start();
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}
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} else {
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bool rewritten = false;
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if (m_dmrNetwork1 != NULL) {
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// Rewrite the slot and/or TG or neither
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for (std::vector<CRewriteTG*>::iterator it = m_dmr1RFRewrites.begin(); it != m_dmr1RFRewrites.end(); ++it) {
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for (std::vector<IRewrite*>::iterator it = m_dmr1RFRewrites.begin(); it != m_dmr1RFRewrites.end(); ++it) {
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bool ret = (*it)->process(data);
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if (ret) {
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rewritten = true;
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@@ -390,7 +372,7 @@ int CDMRGateway::run()
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if (!rewritten) {
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if (m_dmrNetwork2 != NULL) {
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// Rewrite the slot and/or TG or neither
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for (std::vector<CRewriteTG*>::iterator it = m_dmr2RFRewrites.begin(); it != m_dmr2RFRewrites.end(); ++it) {
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for (std::vector<IRewrite*>::iterator it = m_dmr2RFRewrites.begin(); it != m_dmr2RFRewrites.end(); ++it) {
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bool ret = (*it)->process(data);
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if (ret) {
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rewritten = true;
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@@ -433,41 +415,27 @@ int CDMRGateway::run()
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if (m_dmrNetwork1 != NULL) {
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ret = m_dmrNetwork1->read(data);
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if (ret) {
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FLCO flco = data.getFLCO();
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if (flco == FLCO_USER_USER) {
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// Rewrite the slot and/or TG or neither
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bool rewritten = false;
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for (std::vector<IRewrite*>::iterator it = m_dmr1NetRewrites.begin(); it != m_dmr1NetRewrites.end(); ++it) {
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bool ret = (*it)->process(data);
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if (ret) {
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rewritten = true;
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break;
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}
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}
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if (rewritten) {
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unsigned int slotNo = data.getSlotNo();
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unsigned int dstId = data.getDstId();
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FLCO flco = data.getFLCO();
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if (slotNo == 1U && m_dmr1PrivateSlot1) {
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m_repeater->write(data);
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status[slotNo] = DMRGWS_NETWORK1;
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timer[slotNo]->start();
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} else if (slotNo == 2U && m_dmr1PrivateSlot2) {
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m_repeater->write(data);
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status[slotNo] = DMRGWS_NETWORK1;
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timer[slotNo]->start();
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}
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} else {
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// Rewrite the slot and/or TG or neither
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bool rewritten = false;
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for (std::vector<CRewriteTG*>::iterator it = m_dmr1NetRewrites.begin(); it != m_dmr1NetRewrites.end(); ++it) {
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bool ret = (*it)->process(data);
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if (ret) {
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rewritten = true;
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break;
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}
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}
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if (rewritten) {
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unsigned int slotNo = data.getSlotNo();
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unsigned int dstId = data.getDstId();
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// Stop the DMR network from using the same TG as XLX after rewriting
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if (slotNo != m_xlxSlot || dstId != m_xlxTG) {
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if (status[slotNo] == DMRGWS_NONE || status[slotNo] == DMRGWS_NETWORK1) {
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m_repeater->write(data);
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status[slotNo] = DMRGWS_NETWORK1;
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timer[slotNo]->start();
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}
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// Stop the DMR network from using the same TG and slot as XLX after rewriting
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if (flco != FLCO_GROUP || slotNo != m_xlxSlot || dstId != m_xlxTG) {
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if (status[slotNo] == DMRGWS_NONE || status[slotNo] == DMRGWS_NETWORK1) {
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m_repeater->write(data);
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status[slotNo] = DMRGWS_NETWORK1;
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timer[slotNo]->start();
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}
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}
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}
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@@ -477,41 +445,27 @@ int CDMRGateway::run()
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if (m_dmrNetwork2 != NULL) {
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ret = m_dmrNetwork2->read(data);
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if (ret) {
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FLCO flco = data.getFLCO();
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if (flco == FLCO_USER_USER) {
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// Rewrite the slot and/or TG or neither
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bool rewritten = false;
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for (std::vector<IRewrite*>::iterator it = m_dmr2NetRewrites.begin(); it != m_dmr2NetRewrites.end(); ++it) {
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bool ret = (*it)->process(data);
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if (ret) {
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rewritten = true;
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break;
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}
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}
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if (rewritten) {
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unsigned int slotNo = data.getSlotNo();
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unsigned int dstId = data.getDstId();
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FLCO flco = data.getFLCO();
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if (slotNo == 1U && m_dmr2PrivateSlot1) {
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m_repeater->write(data);
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status[slotNo] = DMRGWS_NETWORK2;
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timer[slotNo]->start();
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} else if (slotNo == 2U && m_dmr2PrivateSlot2) {
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m_repeater->write(data);
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status[slotNo] = DMRGWS_NETWORK2;
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timer[slotNo]->start();
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}
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} else {
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// Rewrite the slot and/or TG or neither
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bool rewritten = false;
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for (std::vector<CRewriteTG*>::iterator it = m_dmr2NetRewrites.begin(); it != m_dmr2NetRewrites.end(); ++it) {
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bool ret = (*it)->process(data);
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if (ret) {
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rewritten = true;
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break;
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}
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}
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if (rewritten) {
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unsigned int slotNo = data.getSlotNo();
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unsigned int dstId = data.getDstId();
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// Stop the DMR network from using the same TG as XLX after rewriting
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if (slotNo != m_xlxSlot || dstId != m_xlxTG) {
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if (status[slotNo] == DMRGWS_NONE || status[slotNo] == DMRGWS_NETWORK2) {
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m_repeater->write(data);
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status[slotNo] = DMRGWS_NETWORK2;
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timer[slotNo]->start();
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}
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// Stop the DMR network from using the same TG and slot as XLX after rewriting
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if (flco != FLCO_GROUP || slotNo != m_xlxSlot || dstId != m_xlxTG) {
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if (status[slotNo] == DMRGWS_NONE || status[slotNo] == DMRGWS_NETWORK2) {
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m_repeater->write(data);
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status[slotNo] = DMRGWS_NETWORK2;
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timer[slotNo]->start();
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}
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}
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}
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@@ -578,9 +532,6 @@ int CDMRGateway::run()
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delete m_xlxNetwork;
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}
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delete m_rptRewrite;
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delete m_xlxRewrite;
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delete timer[1U];
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delete timer[2U];
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@@ -654,22 +605,27 @@ bool CDMRGateway::createDMRNetwork1()
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return false;
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}
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std::vector<CRewriteStruct> rewrites = m_conf.getDMRNetwork1TGRewrites();
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for (std::vector<CRewriteStruct>::const_iterator it = rewrites.begin(); it != rewrites.end(); ++it) {
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std::vector<CTGRewriteStruct> tgRewrites = m_conf.getDMRNetwork1TGRewrites();
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for (std::vector<CTGRewriteStruct>::const_iterator it = tgRewrites.begin(); it != tgRewrites.end(); ++it) {
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LogInfo(" TG Rewrite: %u:%u -> %u:%u", (*it).m_fromSlot, (*it).m_fromTG, (*it).m_toSlot, (*it).m_toTG);
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CRewriteTG* netRewrite = new CRewriteTG((*it).m_toSlot, (*it).m_toTG, (*it).m_fromSlot, (*it).m_fromTG);
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CRewriteTG* rfRewrite = new CRewriteTG((*it).m_fromSlot, (*it).m_fromTG, (*it).m_toSlot, (*it).m_toTG);
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CRewriteTG* netTGRewrite = new CRewriteTG((*it).m_toSlot, (*it).m_toTG, (*it).m_fromSlot, (*it).m_fromTG);
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CRewriteTG* rfTGRewrite = new CRewriteTG((*it).m_fromSlot, (*it).m_fromTG, (*it).m_toSlot, (*it).m_toTG);
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m_dmr1NetRewrites.push_back(netRewrite);
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m_dmr1RFRewrites.push_back(rfRewrite);
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m_dmr1NetRewrites.push_back(netTGRewrite);
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m_dmr1RFRewrites.push_back(rfTGRewrite);
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}
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m_dmr1PrivateSlot1 = m_conf.getDMRNetwork1PrivateSlot1();
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m_dmr1PrivateSlot2 = m_conf.getDMRNetwork1PrivateSlot2();
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std::vector<CPCRewriteStruct> pcRewrites = m_conf.getDMRNetwork1PCRewrites();
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for (std::vector<CPCRewriteStruct>::const_iterator it = pcRewrites.begin(); it != pcRewrites.end(); ++it) {
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LogInfo(" PC Rewrite: %u:%u-%u -> %u:%u-%u", (*it).m_fromSlot, (*it).m_fromId, (*it).m_fromId + (*it).m_range - 1U, (*it).m_toSlot, (*it).m_toId, (*it).m_toId + (*it).m_range - 1U);
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LogInfo(" Private slot 1: %s", m_dmr1PrivateSlot1 ? "yes" : "no");
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LogInfo(" Private slot 2: %s", m_dmr1PrivateSlot2 ? "yes" : "no");
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CRewritePC* netPCRewrite = new CRewritePC((*it).m_toSlot, (*it).m_toId, (*it).m_fromSlot, (*it).m_fromId, (*it).m_range);
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CRewritePC* rfPCRewrite = new CRewritePC((*it).m_fromSlot, (*it).m_fromId, (*it).m_toSlot, (*it).m_toId, (*it).m_range);
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m_dmr1NetRewrites.push_back(netPCRewrite);
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m_dmr1RFRewrites.push_back(rfPCRewrite);
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}
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return true;
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}
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@@ -715,22 +671,27 @@ bool CDMRGateway::createDMRNetwork2()
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return false;
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}
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std::vector<CRewriteStruct> rewrites = m_conf.getDMRNetwork2TGRewrites();
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for (std::vector<CRewriteStruct>::const_iterator it = rewrites.begin(); it != rewrites.end(); ++it) {
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std::vector<CTGRewriteStruct> tgRewrites = m_conf.getDMRNetwork2TGRewrites();
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for (std::vector<CTGRewriteStruct>::const_iterator it = tgRewrites.begin(); it != tgRewrites.end(); ++it) {
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LogInfo(" TG Rewrite: %u:%u -> %u:%u", (*it).m_fromSlot, (*it).m_fromTG, (*it).m_toSlot, (*it).m_toTG);
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CRewriteTG* netRewrite = new CRewriteTG((*it).m_toSlot, (*it).m_toTG, (*it).m_fromSlot, (*it).m_fromTG);
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CRewriteTG* rfRewrite = new CRewriteTG((*it).m_fromSlot, (*it).m_fromTG, (*it).m_toSlot, (*it).m_toTG);
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CRewriteTG* netTGRewrite = new CRewriteTG((*it).m_toSlot, (*it).m_toTG, (*it).m_fromSlot, (*it).m_fromTG);
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CRewriteTG* rfTGRewrite = new CRewriteTG((*it).m_fromSlot, (*it).m_fromTG, (*it).m_toSlot, (*it).m_toTG);
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m_dmr2NetRewrites.push_back(netRewrite);
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m_dmr2RFRewrites.push_back(rfRewrite);
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m_dmr2NetRewrites.push_back(netTGRewrite);
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m_dmr2RFRewrites.push_back(rfTGRewrite);
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}
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m_dmr2PrivateSlot1 = m_conf.getDMRNetwork2PrivateSlot1();
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m_dmr2PrivateSlot2 = m_conf.getDMRNetwork2PrivateSlot2();
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std::vector<CPCRewriteStruct> pcRewrites = m_conf.getDMRNetwork2PCRewrites();
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for (std::vector<CPCRewriteStruct>::const_iterator it = pcRewrites.begin(); it != pcRewrites.end(); ++it) {
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LogInfo(" PC Rewrite: %u:%u-%u -> %u:%u-%u", (*it).m_fromSlot, (*it).m_fromId, (*it).m_fromId + (*it).m_range - 1U, (*it).m_toSlot, (*it).m_toId, (*it).m_toId + (*it).m_range - 1U);
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LogInfo(" Private slot 1: %s", m_dmr2PrivateSlot1 ? "yes" : "no");
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LogInfo(" Private slot 2: %s", m_dmr2PrivateSlot2 ? "yes" : "no");
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CRewritePC* netPCRewrite = new CRewritePC((*it).m_toSlot, (*it).m_toId, (*it).m_fromSlot, (*it).m_fromId, (*it).m_range);
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CRewritePC* rfPCRewrite = new CRewritePC((*it).m_fromSlot, (*it).m_fromId, (*it).m_toSlot, (*it).m_toId, (*it).m_range);
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m_dmr2NetRewrites.push_back(netPCRewrite);
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m_dmr2RFRewrites.push_back(rfPCRewrite);
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}
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return true;
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}
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