From 2e257da997344bfbc8261f8324c954415072b756 Mon Sep 17 00:00:00 2001 From: Jonathan Naylor Date: Sun, 4 Jun 2017 15:17:43 +0100 Subject: [PATCH] Add basic rule tracing. --- Conf.cpp | 8 +++++ Conf.h | 2 ++ DMRGateway.cpp | 85 ++++++++++++++++++++++++++++++++++--------------- DMRGateway.h | 1 + DMRGateway.ini | 1 + PassAllPC.cpp | 20 +++++++++--- PassAllPC.h | 3 +- PassAllTG.cpp | 20 +++++++++--- PassAllTG.h | 3 +- RewritePC.cpp | 18 +++++++++-- RewritePC.h | 3 +- RewriteSrc.cpp | 17 ++++++++-- RewriteSrc.h | 3 +- RewriteTG.cpp | 22 ++++++++++--- RewriteTG.h | 3 +- RewriteType.cpp | 21 +++++++++--- RewriteType.h | 3 +- 17 files changed, 177 insertions(+), 56 deletions(-) diff --git a/Conf.cpp b/Conf.cpp index 0f1f10b..d6b86bc 100644 --- a/Conf.cpp +++ b/Conf.cpp @@ -45,6 +45,7 @@ m_rptPort(62032U), m_localAddress("127.0.0.1"), m_localPort(62031U), m_timeout(10U), +m_ruleTrace(false), m_debug(false), m_voiceEnabled(true), m_voiceLanguage("en_GB"), @@ -169,6 +170,8 @@ bool CConf::read() m_localAddress = value; else if (::strcmp(key, "LocalPort") == 0) m_localPort = (unsigned int)::atoi(value); + else if (::strcmp(key, "RuleTrace") == 0) + m_ruleTrace = ::atoi(value) == 1; else if (::strcmp(key, "Debug") == 0) m_debug = ::atoi(value) == 1; } else if (section == SECTION_LOG) { @@ -439,6 +442,11 @@ unsigned int CConf::getTimeout() const return m_timeout; } +bool CConf::getRuleTrace() const +{ + return m_ruleTrace; +} + bool CConf::getDebug() const { return m_debug; diff --git a/Conf.h b/Conf.h index 5e5288d..9f17c37 100644 --- a/Conf.h +++ b/Conf.h @@ -68,6 +68,7 @@ public: unsigned int getRptPort() const; std::string getLocalAddress() const; unsigned int getLocalPort() const; + bool getRuleTrace() const; bool getDebug() const; // The Log section @@ -149,6 +150,7 @@ private: std::string m_localAddress; unsigned int m_localPort; unsigned int m_timeout; + bool m_ruleTrace; bool m_debug; bool m_voiceEnabled; diff --git a/DMRGateway.cpp b/DMRGateway.cpp index 2c148ab..ae940a6 100644 --- a/DMRGateway.cpp +++ b/DMRGateway.cpp @@ -127,6 +127,7 @@ int main(int argc, char** argv) CDMRGateway::CDMRGateway(const std::string& confFile) : m_conf(confFile), +m_ruleTrace(false), m_repeater(NULL), m_dmrNetwork1(NULL), m_dmrNetwork2(NULL), @@ -342,6 +343,9 @@ int CDMRGateway::run() } } + m_ruleTrace = m_conf.getRuleTrace(); + LogInfo("Rule trace: %s", m_ruleTrace ? "yes" : "no"); + CTimer* timer[3U]; timer[1U] = new CTimer(1000U, timeout); timer[2U] = new CTimer(1000U, timeout); @@ -508,6 +512,14 @@ int CDMRGateway::run() } } } else { + unsigned int slotNo = data.getSlotNo(); + unsigned int srcId = data.getSrcId(); + unsigned int dstId = data.getDstId(); + FLCO flco = data.getFLCO(); + + if (m_ruleTrace) + LogDebug("Rule Trace, RF transmission: S%u %u -> %s%u", slotNo, srcId, flco == FLCO_GROUP ? "TG" : "", dstId); + bool rewritten = false; if (m_dmrNetwork1 != NULL) { @@ -521,7 +533,6 @@ int CDMRGateway::run() } if (rewritten) { - unsigned int slotNo = data.getSlotNo(); if (status[slotNo] == DMRGWS_NONE || status[slotNo] == DMRGWS_DMRNETWORK1) { m_dmrNetwork1->write(data); status[slotNo] = DMRGWS_DMRNETWORK1; @@ -542,7 +553,6 @@ int CDMRGateway::run() } if (rewritten) { - unsigned int slotNo = data.getSlotNo(); if (status[slotNo] == DMRGWS_NONE || status[slotNo] == DMRGWS_DMRNETWORK2) { m_dmrNetwork2->write(data); status[slotNo] = DMRGWS_DMRNETWORK2; @@ -551,6 +561,9 @@ int CDMRGateway::run() } } } + + if (!rewritten && m_ruleTrace) + LogDebug("Rule Trace,\tnot matched so rejected"); } } @@ -596,6 +609,14 @@ int CDMRGateway::run() if (m_dmrNetwork1 != NULL) { ret = m_dmrNetwork1->read(data); if (ret) { + unsigned int slotNo = data.getSlotNo(); + unsigned int srcId = data.getSrcId(); + unsigned int dstId = data.getDstId(); + FLCO flco = data.getFLCO(); + + if (m_ruleTrace) + LogDebug("Rule Trace, network 1 transmission: S%u %u -> %s%u", slotNo, srcId, flco == FLCO_GROUP ? "TG" : "", dstId); + // Rewrite the slot and/or TG or neither bool rewritten = false; for (std::vector::iterator it = m_dmr1NetRewrites.begin(); it != m_dmr1NetRewrites.end(); ++it) { @@ -607,13 +628,15 @@ int CDMRGateway::run() } if (rewritten) { - unsigned int slotNo = data.getSlotNo(); if (status[slotNo] == DMRGWS_NONE || status[slotNo] == DMRGWS_DMRNETWORK1) { m_repeater->write(data); status[slotNo] = DMRGWS_DMRNETWORK1; timer[slotNo]->start(); } } + + if (!rewritten && m_ruleTrace) + LogDebug("Rule Trace,\tnot matched so rejected"); } ret = m_dmrNetwork1->wantsBeacon(); @@ -624,6 +647,14 @@ int CDMRGateway::run() if (m_dmrNetwork2 != NULL) { ret = m_dmrNetwork2->read(data); if (ret) { + unsigned int slotNo = data.getSlotNo(); + unsigned int srcId = data.getSrcId(); + unsigned int dstId = data.getDstId(); + FLCO flco = data.getFLCO(); + + if (m_ruleTrace) + LogDebug("Rule Trace, network 2 transmission: S%u %u -> %s%u", slotNo, srcId, flco == FLCO_GROUP ? "TG" : "", dstId); + // Rewrite the slot and/or TG or neither bool rewritten = false; for (std::vector::iterator it = m_dmr2NetRewrites.begin(); it != m_dmr2NetRewrites.end(); ++it) { @@ -635,13 +666,15 @@ int CDMRGateway::run() } if (rewritten) { - unsigned int slotNo = data.getSlotNo(); if (status[slotNo] == DMRGWS_NONE || status[slotNo] == DMRGWS_DMRNETWORK2) { m_repeater->write(data); status[slotNo] = DMRGWS_DMRNETWORK2; timer[slotNo]->start(); } } + + if (!rewritten && m_ruleTrace) + LogDebug("Rule Trace,\tnot matched so rejected"); } ret = m_dmrNetwork2->wantsBeacon(); @@ -836,8 +869,8 @@ bool CDMRGateway::createDMRNetwork1() LogInfo(" Rewrite RF: %u:TG%u-TG%u -> %u:TG%u-TG%u", (*it).m_fromSlot, (*it).m_fromTG, (*it).m_fromTG + (*it).m_range - 1U, (*it).m_toSlot, (*it).m_toTG, (*it).m_toTG + (*it).m_range - 1U); LogInfo(" Rewrite Net: %u:TG%u-TG%u -> %u:TG%u-TG%u", (*it).m_toSlot, (*it).m_toTG, (*it).m_toTG + (*it).m_range - 1U, (*it).m_fromSlot, (*it).m_fromTG, (*it).m_fromTG + (*it).m_range - 1U); - CRewriteTG* rfRewrite = new CRewriteTG("DMR-1", (*it).m_fromSlot, (*it).m_fromTG, (*it).m_toSlot, (*it).m_toTG, (*it).m_range); - CRewriteTG* netRewrite = new CRewriteTG("DMR-1", (*it).m_toSlot, (*it).m_toTG, (*it).m_fromSlot, (*it).m_fromTG, (*it).m_range); + CRewriteTG* rfRewrite = new CRewriteTG("DMR-1", (*it).m_fromSlot, (*it).m_fromTG, (*it).m_toSlot, (*it).m_toTG, (*it).m_range, m_ruleTrace); + CRewriteTG* netRewrite = new CRewriteTG("DMR-1", (*it).m_toSlot, (*it).m_toTG, (*it).m_fromSlot, (*it).m_fromTG, (*it).m_range, m_ruleTrace); m_dmr1RFRewrites.push_back(rfRewrite); m_dmr1NetRewrites.push_back(netRewrite); @@ -847,7 +880,7 @@ bool CDMRGateway::createDMRNetwork1() for (std::vector::const_iterator it = pcRewrites.begin(); it != pcRewrites.end(); ++it) { LogInfo(" Rewrite RF: %u:%u-%u -> %u:%u-%u", (*it).m_fromSlot, (*it).m_fromId, (*it).m_fromId + (*it).m_range - 1U, (*it).m_toSlot, (*it).m_toId, (*it).m_toId + (*it).m_range - 1U); - CRewritePC* rewrite = new CRewritePC("DMR-1", (*it).m_fromSlot, (*it).m_fromId, (*it).m_toSlot, (*it).m_toId, (*it).m_range); + CRewritePC* rewrite = new CRewritePC("DMR-1", (*it).m_fromSlot, (*it).m_fromId, (*it).m_toSlot, (*it).m_toId, (*it).m_range, m_ruleTrace); m_dmr1RFRewrites.push_back(rewrite); } @@ -856,7 +889,7 @@ bool CDMRGateway::createDMRNetwork1() for (std::vector::const_iterator it = typeRewrites.begin(); it != typeRewrites.end(); ++it) { LogInfo(" Rewrite RF: %u:TG%u -> %u:%u", (*it).m_fromSlot, (*it).m_fromTG, (*it).m_toSlot, (*it).m_toId); - CRewriteType* rewrite = new CRewriteType("DMR-1", (*it).m_fromSlot, (*it).m_fromTG, (*it).m_toSlot, (*it).m_toId); + CRewriteType* rewrite = new CRewriteType("DMR-1", (*it).m_fromSlot, (*it).m_fromTG, (*it).m_toSlot, (*it).m_toId, m_ruleTrace); m_dmr1RFRewrites.push_back(rewrite); } @@ -865,7 +898,7 @@ bool CDMRGateway::createDMRNetwork1() for (std::vector::const_iterator it = srcRewrites.begin(); it != srcRewrites.end(); ++it) { LogInfo(" Rewrite Net: %u:%u-%u -> %u:TG%u", (*it).m_fromSlot, (*it).m_fromId, (*it).m_fromId + (*it).m_range - 1U, (*it).m_toSlot, (*it).m_toTG); - CRewriteSrc* rewrite = new CRewriteSrc("DMR-1", (*it).m_fromSlot, (*it).m_fromId, (*it).m_toSlot, (*it).m_toTG, (*it).m_range); + CRewriteSrc* rewrite = new CRewriteSrc("DMR-1", (*it).m_fromSlot, (*it).m_fromId, (*it).m_toSlot, (*it).m_toTG, (*it).m_range, m_ruleTrace); m_dmr1NetRewrites.push_back(rewrite); } @@ -874,8 +907,8 @@ bool CDMRGateway::createDMRNetwork1() for (std::vector::const_iterator it = tgPassAll.begin(); it != tgPassAll.end(); ++it) { LogInfo(" Pass All TG: %u", *it); - CPassAllTG* rfPassAllTG = new CPassAllTG("DMR-1", *it); - CPassAllTG* netPassAllTG = new CPassAllTG("DMR-1", *it); + CPassAllTG* rfPassAllTG = new CPassAllTG("DMR-1", *it, m_ruleTrace); + CPassAllTG* netPassAllTG = new CPassAllTG("DMR-1", *it, m_ruleTrace); m_dmr1RFRewrites.push_back(rfPassAllTG); m_dmr1NetRewrites.push_back(netPassAllTG); @@ -885,8 +918,8 @@ bool CDMRGateway::createDMRNetwork1() for (std::vector::const_iterator it = pcPassAll.begin(); it != pcPassAll.end(); ++it) { LogInfo(" Pass All PC: %u", *it); - CPassAllPC* rfPassAllPC = new CPassAllPC("DMR-1", *it); - CPassAllPC* netPassAllPC = new CPassAllPC("DMR-1", *it); + CPassAllPC* rfPassAllPC = new CPassAllPC("DMR-1", *it, m_ruleTrace); + CPassAllPC* netPassAllPC = new CPassAllPC("DMR-1", *it, m_ruleTrace); m_dmr1RFRewrites.push_back(rfPassAllPC); m_dmr1NetRewrites.push_back(netPassAllPC); @@ -944,8 +977,8 @@ bool CDMRGateway::createDMRNetwork2() LogInfo(" Rewrite RF: %u:TG%u-TG%u -> %u:TG%u-TG%u", (*it).m_fromSlot, (*it).m_fromTG, (*it).m_fromTG + (*it).m_range - 1U, (*it).m_toSlot, (*it).m_toTG, (*it).m_toTG + (*it).m_range - 1U); LogInfo(" Rewrite Net: %u:TG%u-TG%u -> %u:TG%u-TG%u", (*it).m_toSlot, (*it).m_toTG, (*it).m_toTG + (*it).m_range - 1U, (*it).m_fromSlot, (*it).m_fromTG, (*it).m_fromTG + (*it).m_range - 1U); - CRewriteTG* rfRewrite = new CRewriteTG("DMR-2", (*it).m_fromSlot, (*it).m_fromTG, (*it).m_toSlot, (*it).m_toTG, (*it).m_range); - CRewriteTG* netRewrite = new CRewriteTG("DMR-2", (*it).m_toSlot, (*it).m_toTG, (*it).m_fromSlot, (*it).m_fromTG, (*it).m_range); + CRewriteTG* rfRewrite = new CRewriteTG("DMR-2", (*it).m_fromSlot, (*it).m_fromTG, (*it).m_toSlot, (*it).m_toTG, (*it).m_range, m_ruleTrace); + CRewriteTG* netRewrite = new CRewriteTG("DMR-2", (*it).m_toSlot, (*it).m_toTG, (*it).m_fromSlot, (*it).m_fromTG, (*it).m_range, m_ruleTrace); m_dmr2RFRewrites.push_back(rfRewrite); m_dmr2NetRewrites.push_back(netRewrite); @@ -955,7 +988,7 @@ bool CDMRGateway::createDMRNetwork2() for (std::vector::const_iterator it = pcRewrites.begin(); it != pcRewrites.end(); ++it) { LogInfo(" Rewrite RF: %u:%u-%u -> %u:%u-%u", (*it).m_fromSlot, (*it).m_fromId, (*it).m_fromId + (*it).m_range - 1U, (*it).m_toSlot, (*it).m_toId, (*it).m_toId + (*it).m_range - 1U); - CRewritePC* rewrite = new CRewritePC("DMR-2", (*it).m_fromSlot, (*it).m_fromId, (*it).m_toSlot, (*it).m_toId, (*it).m_range); + CRewritePC* rewrite = new CRewritePC("DMR-2", (*it).m_fromSlot, (*it).m_fromId, (*it).m_toSlot, (*it).m_toId, (*it).m_range, m_ruleTrace); m_dmr2RFRewrites.push_back(rewrite); } @@ -964,7 +997,7 @@ bool CDMRGateway::createDMRNetwork2() for (std::vector::const_iterator it = typeRewrites.begin(); it != typeRewrites.end(); ++it) { LogInfo(" Rewrite RF: %u:TG%u -> %u:%u", (*it).m_fromSlot, (*it).m_fromTG, (*it).m_toSlot, (*it).m_toId); - CRewriteType* rewrite = new CRewriteType("DMR-2", (*it).m_fromSlot, (*it).m_fromTG, (*it).m_toSlot, (*it).m_toId); + CRewriteType* rewrite = new CRewriteType("DMR-2", (*it).m_fromSlot, (*it).m_fromTG, (*it).m_toSlot, (*it).m_toId, m_ruleTrace); m_dmr2RFRewrites.push_back(rewrite); } @@ -973,7 +1006,7 @@ bool CDMRGateway::createDMRNetwork2() for (std::vector::const_iterator it = srcRewrites.begin(); it != srcRewrites.end(); ++it) { LogInfo(" Rewrite Net: %u:%u-%u -> %u:TG%u", (*it).m_fromSlot, (*it).m_fromId, (*it).m_fromId + (*it).m_range - 1U, (*it).m_toSlot, (*it).m_toTG); - CRewriteSrc* rewrite = new CRewriteSrc("DMR-2", (*it).m_fromSlot, (*it).m_fromId, (*it).m_toSlot, (*it).m_toTG, (*it).m_range); + CRewriteSrc* rewrite = new CRewriteSrc("DMR-2", (*it).m_fromSlot, (*it).m_fromId, (*it).m_toSlot, (*it).m_toTG, (*it).m_range, m_ruleTrace); m_dmr2NetRewrites.push_back(rewrite); } @@ -982,8 +1015,8 @@ bool CDMRGateway::createDMRNetwork2() for (std::vector::const_iterator it = tgPassAll.begin(); it != tgPassAll.end(); ++it) { LogInfo(" Pass All TG: %u", *it); - CPassAllTG* rfPassAllTG = new CPassAllTG("DMR-2", *it); - CPassAllTG* netPassAllTG = new CPassAllTG("DMR-2", *it); + CPassAllTG* rfPassAllTG = new CPassAllTG("DMR-2", *it, m_ruleTrace); + CPassAllTG* netPassAllTG = new CPassAllTG("DMR-2", *it, m_ruleTrace); m_dmr2RFRewrites.push_back(rfPassAllTG); m_dmr2NetRewrites.push_back(netPassAllTG); @@ -993,8 +1026,8 @@ bool CDMRGateway::createDMRNetwork2() for (std::vector::const_iterator it = pcPassAll.begin(); it != pcPassAll.end(); ++it) { LogInfo(" Pass All PC: %u", *it); - CPassAllPC* rfPassAllPC = new CPassAllPC("DMR-2", *it); - CPassAllPC* netPassAllPC = new CPassAllPC("DMR-2", *it); + CPassAllPC* rfPassAllPC = new CPassAllPC("DMR-2", *it, m_ruleTrace); + CPassAllPC* netPassAllPC = new CPassAllPC("DMR-2", *it, m_ruleTrace); m_dmr2RFRewrites.push_back(rfPassAllPC); m_dmr2NetRewrites.push_back(netPassAllPC); @@ -1055,8 +1088,8 @@ bool CDMRGateway::createXLXNetwork1() if (m_xlx1Startup != 4000U) LogInfo(" Startup: %u", m_xlx1Startup); - m_rpt1Rewrite = new CRewriteTG("XLX-1", XLX_SLOT, XLX_TG, m_xlx1Slot, m_xlx1TG, 1U); - m_xlx1Rewrite = new CRewriteTG("XLX-1", m_xlx1Slot, m_xlx1TG, XLX_SLOT, XLX_TG, 1U); + m_rpt1Rewrite = new CRewriteTG("XLX-1", XLX_SLOT, XLX_TG, m_xlx1Slot, m_xlx1TG, 1U, false); + m_xlx1Rewrite = new CRewriteTG("XLX-1", m_xlx1Slot, m_xlx1TG, XLX_SLOT, XLX_TG, 1U, false); return true; } @@ -1113,8 +1146,8 @@ bool CDMRGateway::createXLXNetwork2() if (m_xlx2Startup != 4000U) LogInfo(" Startup: %u", m_xlx2Startup); - m_rpt2Rewrite = new CRewriteTG("XLX-2", XLX_SLOT, XLX_TG, m_xlx2Slot, m_xlx2TG, 1U); - m_xlx2Rewrite = new CRewriteTG("XLX-2", m_xlx2Slot, m_xlx2TG, XLX_SLOT, XLX_TG, 1U); + m_rpt2Rewrite = new CRewriteTG("XLX-2", XLX_SLOT, XLX_TG, m_xlx2Slot, m_xlx2TG, 1U, false); + m_xlx2Rewrite = new CRewriteTG("XLX-2", m_xlx2Slot, m_xlx2TG, XLX_SLOT, XLX_TG, 1U, false); return true; } diff --git a/DMRGateway.h b/DMRGateway.h index 3f3afd9..bae8be1 100644 --- a/DMRGateway.h +++ b/DMRGateway.h @@ -38,6 +38,7 @@ public: private: CConf m_conf; + bool m_ruleTrace; IRepeaterProtocol* m_repeater; CDMRNetwork* m_dmrNetwork1; CDMRNetwork* m_dmrNetwork2; diff --git a/DMRGateway.ini b/DMRGateway.ini index 596589a..ed824ea 100644 --- a/DMRGateway.ini +++ b/DMRGateway.ini @@ -4,6 +4,7 @@ RptAddress=127.0.0.1 RptPort=62032 LocalAddress=127.0.0.1 LocalPort=62031 +RuleTrace=0 Daemon=0 Debug=0 diff --git a/PassAllPC.cpp b/PassAllPC.cpp index 0094093..8852efb 100644 --- a/PassAllPC.cpp +++ b/PassAllPC.cpp @@ -19,13 +19,15 @@ #include "PassAllPC.h" #include "DMRDefines.h" +#include "Log.h" #include #include -CPassAllPC::CPassAllPC(const char* name, unsigned int slot) : +CPassAllPC::CPassAllPC(const char* name, unsigned int slot, bool trace) : m_name(name), -m_slot(slot) +m_slot(slot), +m_trace(trace) { assert(slot == 1U || slot == 2U); } @@ -36,12 +38,22 @@ CPassAllPC::~CPassAllPC() bool CPassAllPC::processRF(CDMRData& data) { - return process(data); + bool ret = process(data); + + if (m_trace) + LogDebug("Rule Trace,\tPassAllPC %s Slot=%u: %s", m_name, m_slot, ret ? "matched" : "not matched"); + + return ret; } bool CPassAllPC::processNet(CDMRData& data) { - return process(data); + bool ret = process(data); + + if (m_trace) + LogDebug("Rule Trace,\tPassAllPC %s Slot=%u: %s", m_name, m_slot, ret ? "matched" : "not matched"); + + return ret; } bool CPassAllPC::process(CDMRData& data) diff --git a/PassAllPC.h b/PassAllPC.h index cfb3afb..cee8729 100644 --- a/PassAllPC.h +++ b/PassAllPC.h @@ -24,7 +24,7 @@ class CPassAllPC : public IRewrite { public: - CPassAllPC(const char* name, unsigned int slot); + CPassAllPC(const char* name, unsigned int slot, bool trace); virtual ~CPassAllPC(); virtual bool processRF(CDMRData& data); @@ -33,6 +33,7 @@ public: private: const char* m_name; unsigned int m_slot; + bool m_trace; bool process(CDMRData& data); }; diff --git a/PassAllTG.cpp b/PassAllTG.cpp index ff5ad81..a11697d 100644 --- a/PassAllTG.cpp +++ b/PassAllTG.cpp @@ -19,13 +19,15 @@ #include "PassAllTG.h" #include "DMRDefines.h" +#include "Log.h" #include #include -CPassAllTG::CPassAllTG(const char* name, unsigned int slot) : +CPassAllTG::CPassAllTG(const char* name, unsigned int slot, bool trace) : m_name(name), -m_slot(slot) +m_slot(slot), +m_trace(trace) { assert(slot == 1U || slot == 2U); } @@ -36,12 +38,22 @@ CPassAllTG::~CPassAllTG() bool CPassAllTG::processRF(CDMRData& data) { - return process(data); + bool ret = process(data); + + if (m_trace) + LogDebug("Rule Trace,\tPassAllTG %s Slot=%u: %s", m_name, m_slot, ret ? "matched" : "not matched"); + + return ret; } bool CPassAllTG::processNet(CDMRData& data) { - return process(data); + bool ret = process(data); + + if (m_trace) + LogDebug("Rule Trace,\tPassAllTG %s Slot=%u: %s", m_name, m_slot, ret ? "matched" : "not matched"); + + return ret; } bool CPassAllTG::process(CDMRData& data) diff --git a/PassAllTG.h b/PassAllTG.h index e17d7b6..9780d61 100644 --- a/PassAllTG.h +++ b/PassAllTG.h @@ -24,7 +24,7 @@ class CPassAllTG : public IRewrite { public: - CPassAllTG(const char* name, unsigned int slot); + CPassAllTG(const char* name, unsigned int slot, bool trace); virtual ~CPassAllTG(); virtual bool processRF(CDMRData& data); @@ -33,6 +33,7 @@ public: private: const char* m_name; unsigned int m_slot; + bool m_trace; bool process(CDMRData& data); }; diff --git a/RewritePC.cpp b/RewritePC.cpp index e3b281e..b4f6246 100644 --- a/RewritePC.cpp +++ b/RewritePC.cpp @@ -20,17 +20,19 @@ #include "DMRDefines.h" #include "DMRFullLC.h" +#include "Log.h" #include #include -CRewritePC::CRewritePC(const char* name, unsigned int fromSlot, unsigned int fromId, unsigned int toSlot, unsigned int toId, unsigned int range) : +CRewritePC::CRewritePC(const char* name, unsigned int fromSlot, unsigned int fromId, unsigned int toSlot, unsigned int toId, unsigned int range, bool trace) : m_name(name), m_fromSlot(fromSlot), m_fromIdStart(fromId), m_fromIdEnd(fromId + range), m_toSlot(toSlot), m_toIdStart(toId), +m_trace(trace), m_lc(FLCO_USER_USER, 0U, 0U), m_embeddedLC() { @@ -44,12 +46,22 @@ CRewritePC::~CRewritePC() bool CRewritePC::processRF(CDMRData& data) { - return process(data); + bool ret = process(data); + + if (m_trace) + LogDebug("Rule Trace,\tRewritePC %s Slot=%u Dst=%u-%u: %s", m_name, m_fromSlot, m_fromIdStart, m_fromIdEnd, ret ? "matched" : "not matched"); + + return ret; } bool CRewritePC::processNet(CDMRData& data) { - return process(data); + bool ret = process(data); + + if (m_trace) + LogDebug("Rule Trace,\tRewritePC %s Slot=%u Dst=%u-%u: %s", m_name, m_fromSlot, m_fromIdStart, m_fromIdEnd, ret ? "matched" : "not matched"); + + return ret; } bool CRewritePC::process(CDMRData& data) diff --git a/RewritePC.h b/RewritePC.h index 550ad71..d5872c3 100644 --- a/RewritePC.h +++ b/RewritePC.h @@ -26,7 +26,7 @@ class CRewritePC : public IRewrite { public: - CRewritePC(const char* name, unsigned int fromSlot, unsigned int fromId, unsigned int toSlot, unsigned int toId, unsigned int range); + CRewritePC(const char* name, unsigned int fromSlot, unsigned int fromId, unsigned int toSlot, unsigned int toId, unsigned int range, bool trace); virtual ~CRewritePC(); virtual bool processRF(CDMRData& data); @@ -39,6 +39,7 @@ private: unsigned int m_fromIdEnd; unsigned int m_toSlot; unsigned int m_toIdStart; + bool m_trace; CDMRLC m_lc; CDMREmbeddedData m_embeddedLC; diff --git a/RewriteSrc.cpp b/RewriteSrc.cpp index 8aa9a62..5b470fe 100644 --- a/RewriteSrc.cpp +++ b/RewriteSrc.cpp @@ -25,13 +25,14 @@ #include #include -CRewriteSrc::CRewriteSrc(const char* name, unsigned int fromSlot, unsigned int fromId, unsigned int toSlot, unsigned int toTG, unsigned int range) : +CRewriteSrc::CRewriteSrc(const char* name, unsigned int fromSlot, unsigned int fromId, unsigned int toSlot, unsigned int toTG, unsigned int range, bool trace) : m_name(name), m_fromSlot(fromSlot), m_fromIdStart(fromId), m_fromIdEnd(fromId + range), m_toSlot(toSlot), m_toTG(toTG), +m_trace(trace), m_lc(FLCO_GROUP, 0U, toTG), m_embeddedLC() { @@ -47,12 +48,22 @@ CRewriteSrc::~CRewriteSrc() bool CRewriteSrc::processRF(CDMRData& data) { - return process(data); + bool ret = process(data); + + if (m_trace) + LogDebug("Rule Trace,\tRewriteSrc %s Slot=%u Src=%u-%u: %s", m_name, m_fromSlot, m_fromIdStart, m_fromIdEnd, ret ? "matched" : "not matched"); + + return ret; } bool CRewriteSrc::processNet(CDMRData& data) { - return process(data); + bool ret = process(data); + + if (m_trace) + LogDebug("Rule Trace,\tRewriteSrc %s Slot=%u Src=%u-%u: %s", m_name, m_fromSlot, m_fromIdStart, m_fromIdEnd, ret ? "matched" : "not matched"); + + return ret; } bool CRewriteSrc::process(CDMRData& data) diff --git a/RewriteSrc.h b/RewriteSrc.h index d68ef79..3bc2325 100644 --- a/RewriteSrc.h +++ b/RewriteSrc.h @@ -26,7 +26,7 @@ class CRewriteSrc : public IRewrite { public: - CRewriteSrc(const char* name, unsigned int fromSlot, unsigned int fromId, unsigned int toSlot, unsigned int toTG, unsigned int range); + CRewriteSrc(const char* name, unsigned int fromSlot, unsigned int fromId, unsigned int toSlot, unsigned int toTG, unsigned int range, bool trace); virtual ~CRewriteSrc(); virtual bool processRF(CDMRData& data); @@ -39,6 +39,7 @@ private: unsigned int m_fromIdEnd; unsigned int m_toSlot; unsigned int m_toTG; + bool m_trace; CDMRLC m_lc; CDMREmbeddedData m_embeddedLC; diff --git a/RewriteTG.cpp b/RewriteTG.cpp index 8f44e4a..1b005e9 100644 --- a/RewriteTG.cpp +++ b/RewriteTG.cpp @@ -20,17 +20,19 @@ #include "DMRDefines.h" #include "DMRFullLC.h" +#include "Log.h" #include #include -CRewriteTG::CRewriteTG(const char* name, unsigned int fromSlot, unsigned int fromTG, unsigned int toSlot, unsigned int toTG, unsigned int range) : +CRewriteTG::CRewriteTG(const char* name, unsigned int fromSlot, unsigned int fromTG, unsigned int toSlot, unsigned int toTG, unsigned int range, bool trace) : m_name(name), m_fromSlot(fromSlot), m_fromTGStart(fromTG), m_fromTGEnd(fromTG + range), m_toSlot(toSlot), m_toTGStart(toTG), +m_trace(trace), m_lc(FLCO_GROUP, 0U, toTG), m_embeddedLC() { @@ -44,18 +46,28 @@ CRewriteTG::~CRewriteTG() bool CRewriteTG::processRF(CDMRData& data) { - return process(data); + bool ret = process(data); + + if (m_trace) + LogDebug("Rule Trace,\tRewriteTG %s Slot=%u Dst=TG%u-TG%u: %s", m_name, m_fromSlot, m_fromTGStart, m_fromTGEnd, ret ? "matched" : "not matched"); + + return ret; } bool CRewriteTG::processNet(CDMRData& data) { - return process(data); + bool ret = process(data); + + if (m_trace) + LogDebug("Rule Trace,\tRewriteTG %s Slot=%u Dst=TG%u-TG%u: %s", m_name, m_fromSlot, m_fromTGStart, m_fromTGEnd, ret ? "matched" : "not matched"); + + return ret; } bool CRewriteTG::process(CDMRData& data) { - FLCO flco = data.getFLCO(); - unsigned int dstId = data.getDstId(); + FLCO flco = data.getFLCO(); + unsigned int dstId = data.getDstId(); unsigned int slotNo = data.getSlotNo(); if (flco != FLCO_GROUP || slotNo != m_fromSlot || dstId < m_fromTGStart || dstId >= m_fromTGEnd) diff --git a/RewriteTG.h b/RewriteTG.h index 5f2a7f8..1b61799 100644 --- a/RewriteTG.h +++ b/RewriteTG.h @@ -26,7 +26,7 @@ class CRewriteTG : public IRewrite { public: - CRewriteTG(const char*name, unsigned int fromSlot, unsigned int fromTG, unsigned int toSlot, unsigned int toTG, unsigned int range); + CRewriteTG(const char*name, unsigned int fromSlot, unsigned int fromTG, unsigned int toSlot, unsigned int toTG, unsigned int range, bool trace); virtual ~CRewriteTG(); virtual bool processRF(CDMRData& data); @@ -39,6 +39,7 @@ private: unsigned int m_fromTGEnd; unsigned int m_toSlot; unsigned int m_toTGStart; + bool m_trace; CDMRLC m_lc; CDMREmbeddedData m_embeddedLC; diff --git a/RewriteType.cpp b/RewriteType.cpp index a3936da..6f277cf 100644 --- a/RewriteType.cpp +++ b/RewriteType.cpp @@ -25,12 +25,13 @@ #include #include -CRewriteType::CRewriteType(const char* name, unsigned int fromSlot, unsigned int fromTG, unsigned int toSlot, unsigned int toId) : +CRewriteType::CRewriteType(const char* name, unsigned int fromSlot, unsigned int fromTG, unsigned int toSlot, unsigned int toId, bool trace) : m_name(name), m_fromSlot(fromSlot), m_fromTG(fromTG), m_toSlot(toSlot), m_toId(toId), +m_trace(trace), m_lc(FLCO_USER_USER, 0U, toId), m_embeddedLC() { @@ -44,18 +45,28 @@ CRewriteType::~CRewriteType() bool CRewriteType::processRF(CDMRData& data) { - return process(data); + bool ret = process(data); + + if (m_trace) + LogDebug("Rule Trace,\tRewriteType %s Slot=%u Dst=TG%u: %s", m_name, m_fromSlot, m_fromTG, ret ? "matched" : "not matched"); + + return ret; } bool CRewriteType::processNet(CDMRData& data) { - return process(data); + bool ret = process(data); + + if (m_trace) + LogDebug("Rule Trace,\tRewriteType %s Slot=%u Dst=TG%u: %s", m_name, m_fromSlot, m_fromTG, ret ? "matched" : "not matched"); + + return ret; } bool CRewriteType::process(CDMRData& data) { - FLCO flco = data.getFLCO(); - unsigned int dstId = data.getDstId(); + FLCO flco = data.getFLCO(); + unsigned int dstId = data.getDstId(); unsigned int slotNo = data.getSlotNo(); if (flco != FLCO_GROUP || slotNo != m_fromSlot || dstId != m_fromTG) diff --git a/RewriteType.h b/RewriteType.h index c8de2f2..ccac537 100644 --- a/RewriteType.h +++ b/RewriteType.h @@ -26,7 +26,7 @@ class CRewriteType : public IRewrite { public: - CRewriteType(const char* name, unsigned int fromSlot, unsigned int fromTG, unsigned int toSlot, unsigned int toId); + CRewriteType(const char* name, unsigned int fromSlot, unsigned int fromTG, unsigned int toSlot, unsigned int toId, bool trace); virtual ~CRewriteType(); virtual bool processRF(CDMRData& data); @@ -38,6 +38,7 @@ private: unsigned int m_fromTG; unsigned int m_toSlot; unsigned int m_toId; + bool m_trace; CDMRLC m_lc; CDMREmbeddedData m_embeddedLC;