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https://github.com/g4klx/DMRGateway
synced 2026-02-05 13:55:42 +08:00
Add optional names for each network for use in the log,
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@@ -25,7 +25,7 @@
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#include <cstdio>
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#include <cassert>
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CRewriteSrc::CRewriteSrc(const char* name, unsigned int fromSlot, unsigned int fromId, unsigned int toSlot, unsigned int toTG, unsigned int range) :
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CRewriteSrc::CRewriteSrc(const std::string& name, unsigned int fromSlot, unsigned int fromId, unsigned int toSlot, unsigned int toTG, unsigned int range) :
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m_name(name),
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m_fromSlot(fromSlot),
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m_fromIdStart(fromId),
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@@ -53,7 +53,7 @@ bool CRewriteSrc::process(CDMRData& data, bool trace)
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if (flco != FLCO_USER_USER || slotNo != m_fromSlot || srcId < m_fromIdStart || srcId > m_fromIdEnd) {
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if (trace)
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LogDebug("Rule Trace,\tRewriteSrc from %s Slot=%u Src=%u-%u: not matched", m_name, m_fromSlot, m_fromIdStart, m_fromIdEnd);
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LogDebug("Rule Trace,\tRewriteSrc from %s Slot=%u Src=%u-%u: not matched", m_name.c_str(), m_fromSlot, m_fromIdStart, m_fromIdEnd);
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return false;
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}
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@@ -82,8 +82,8 @@ bool CRewriteSrc::process(CDMRData& data, bool trace)
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}
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if (trace) {
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LogDebug("Rule Trace,\tRewriteSrc from %s Slot=%u Src=%u-%u: matched", m_name, m_fromSlot, m_fromIdStart, m_fromIdEnd);
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LogDebug("Rule Trace,\tRewriteSrc to %s Slot=%u Dst=TG%u", m_name, m_toSlot, m_toTG);
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LogDebug("Rule Trace,\tRewriteSrc from %s Slot=%u Src=%u-%u: matched", m_name.c_str(), m_fromSlot, m_fromIdStart, m_fromIdEnd);
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LogDebug("Rule Trace,\tRewriteSrc to %s Slot=%u Dst=TG%u", m_name.c_str(), m_toSlot, m_toTG);
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}
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return true;
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