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https://github.com/g4klx/DMRGateway
synced 2025-12-22 06:05:36 +08:00
Add optional names for each network for use in the log,
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@@ -25,7 +25,7 @@
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#include <cstdio>
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#include <cassert>
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CRewriteType::CRewriteType(const char* name, unsigned int fromSlot, unsigned int fromTG, unsigned int toSlot, unsigned int toId) :
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CRewriteType::CRewriteType(const std::string& name, unsigned int fromSlot, unsigned int fromTG, unsigned int toSlot, unsigned int toId) :
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m_name(name),
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m_fromSlot(fromSlot),
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m_fromTG(fromTG),
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@@ -50,7 +50,7 @@ bool CRewriteType::process(CDMRData& data, bool trace)
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if (flco != FLCO_GROUP || slotNo != m_fromSlot || dstId != m_fromTG) {
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if (trace)
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LogDebug("Rule Trace,\tRewriteType %s Slot=%u Dst=TG%u: not matched", m_name, m_fromSlot, m_fromTG);
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LogDebug("Rule Trace,\tRewriteType %s Slot=%u Dst=TG%u: not matched", m_name.c_str(), m_fromSlot, m_fromTG);
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return false;
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}
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@@ -79,7 +79,7 @@ bool CRewriteType::process(CDMRData& data, bool trace)
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}
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if (trace)
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LogDebug("Rule Trace,\tRewriteType %s Slot=%u Dst=TG%u: matched", m_name, m_fromSlot, m_fromTG);
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LogDebug("Rule Trace,\tRewriteType %s Slot=%u Dst=TG%u: matched", m_name.c_str(), m_fromSlot, m_fromTG);
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return true;
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}
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