diff --git a/DMRGateway.ini b/DMRGateway.ini
index a0266e5..d9b339d 100644
--- a/DMRGateway.ini
+++ b/DMRGateway.ini
@@ -71,7 +71,7 @@ SrcRewrite=1,9990,1,9990,1
 # Reflector status returns
 SrcRewrite=2,4000,2,9,1001
 # Dynamic rewriting of slot 2 TGs 90-999999 to TG9 to emulate reflector behaviour
-TGDynRewrite=2,90,4000,5000,9,999910,9900
+TGDynRewrite=2,90,4000,5000,9,999910,9990
 # Pass all of the other private traffic on slot 1 and slot 2
 PassAllPC=1
 PassAllPC=2
diff --git a/RewriteDynTGRF.cpp b/RewriteDynTGRF.cpp
index 805938c..1af6d20 100644
--- a/RewriteDynTGRF.cpp
+++ b/RewriteDynTGRF.cpp
@@ -107,9 +107,9 @@ PROCESS_RESULT CRewriteDynTGRF::process(CDMRData& data, bool trace)
 
 	if (std::find(m_exclTGs.cbegin(), m_exclTGs.cend(), dstId) != m_exclTGs.cend()) {
 		if (trace)
-			LogDebug("Rule Trace,\tRewriteDynTGRF from %s Slot=%u Dst=%u: matched", m_name.c_str(), m_slot, dstId);
+			LogDebug("Rule Trace,\tRewriteDynTGRF from %s Slot=%u Dst=%u: not matched", m_name.c_str(), m_slot, dstId);
 
-		return RESULT_IGNORED;
+		return RESULT_UNMATCHED;
 	}
 
 	if (slotNo == m_slot && dstId >= m_fromTGStart && dstId <= m_fromTGEnd) {