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https://github.com/g4klx/DMRGateway
synced 2025-12-21 05:25:40 +08:00
Allow for more rewrite processing options.
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@@ -1,5 +1,5 @@
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/*
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* Copyright (C) 2017 by Jonathan Naylor G4KLX
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* Copyright (C) 2017,2020 by Jonathan Naylor G4KLX
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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@@ -42,7 +42,7 @@ CRewritePC::~CRewritePC()
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{
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}
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bool CRewritePC::process(CDMRData& data, bool trace)
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PROCESS_RESULT CRewritePC::process(CDMRData& data, bool trace)
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{
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FLCO flco = data.getFLCO();
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unsigned int dstId = data.getDstId();
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@@ -52,7 +52,7 @@ bool CRewritePC::process(CDMRData& data, bool trace)
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if (trace)
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LogDebug("Rule Trace,\tRewritePC from %s Slot=%u Dst=%u-%u: not matched", m_name.c_str(), m_fromSlot, m_fromIdStart, m_fromIdEnd);
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return false;
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return RESULT_UNMATCHED;
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}
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if (m_fromSlot != m_toSlot)
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@@ -70,5 +70,5 @@ bool CRewritePC::process(CDMRData& data, bool trace)
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LogDebug("Rule Trace,\tRewritePC to %s Slot=%u Dst=%u-%u", m_name.c_str(), m_toSlot, m_toIdStart, m_toIdEnd);
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}
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return true;
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return RESULT_MATCHED;
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}
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