mirror of
https://github.com/g4klx/DMRGateway
synced 2025-12-20 21:25:37 +08:00
Merge branch 'master' into DynTG
This commit is contained in:
20
Conf.cpp
20
Conf.cpp
@@ -381,13 +381,15 @@ bool CConf::read()
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char* p1 = ::strtok(value, ", ");
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char* p2 = ::strtok(NULL, ", ");
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char* p3 = ::strtok(NULL, ", ");
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char* p4 = ::strtok(NULL, " \r\n");
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char* p4 = ::strtok(NULL, ", \r\n");
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if (p1 != NULL && p2 != NULL && p3 != NULL && p4 != NULL) {
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CTypeRewriteStruct rewrite;
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rewrite.m_fromSlot = ::atoi(p1);
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rewrite.m_fromTG = ::atoi(p2);
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rewrite.m_toSlot = ::atoi(p3);
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rewrite.m_toId = ::atoi(p4);
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char* p5 = ::strtok(NULL, " \r\n");
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rewrite.m_range = p5 != NULL ? ::atoi(p5) : 1;
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m_dmrNetwork1TypeRewrites.push_back(rewrite);
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}
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} else if (::strncmp(key, "SrcRewrite", 10U) == 0) {
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@@ -501,13 +503,15 @@ bool CConf::read()
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char* p1 = ::strtok(value, ", ");
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char* p2 = ::strtok(NULL, ", ");
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char* p3 = ::strtok(NULL, ", ");
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char* p4 = ::strtok(NULL, " \r\n");
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char* p4 = ::strtok(NULL, ", \r\n");
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if (p1 != NULL && p2 != NULL && p3 != NULL && p4 != NULL) {
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CTypeRewriteStruct rewrite;
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rewrite.m_fromSlot = ::atoi(p1);
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rewrite.m_fromTG = ::atoi(p2);
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rewrite.m_toSlot = ::atoi(p3);
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rewrite.m_toId = ::atoi(p4);
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char* p5 = ::strtok(NULL, " \r\n");
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rewrite.m_range = p5 != NULL ? ::atoi(p5) : 1;
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m_dmrNetwork2TypeRewrites.push_back(rewrite);
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}
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} else if (::strncmp(key, "SrcRewrite", 10U) == 0) {
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@@ -621,13 +625,15 @@ bool CConf::read()
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char* p1 = ::strtok(value, ", ");
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char* p2 = ::strtok(NULL, ", ");
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char* p3 = ::strtok(NULL, ", ");
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char* p4 = ::strtok(NULL, " \r\n");
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char* p4 = ::strtok(NULL, ", \r\n");
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if (p1 != NULL && p2 != NULL && p3 != NULL && p4 != NULL) {
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CTypeRewriteStruct rewrite;
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rewrite.m_fromSlot = ::atoi(p1);
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rewrite.m_fromTG = ::atoi(p2);
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rewrite.m_toSlot = ::atoi(p3);
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rewrite.m_toId = ::atoi(p4);
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char* p5 = ::strtok(NULL, " \r\n");
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rewrite.m_range = p5 != NULL ? ::atoi(p5) : 1;
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m_dmrNetwork3TypeRewrites.push_back(rewrite);
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}
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} else if (::strncmp(key, "SrcRewrite", 10U) == 0) {
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@@ -741,13 +747,15 @@ bool CConf::read()
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char* p1 = ::strtok(value, ", ");
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char* p2 = ::strtok(NULL, ", ");
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char* p3 = ::strtok(NULL, ", ");
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char* p4 = ::strtok(NULL, " \r\n");
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char* p4 = ::strtok(NULL, ", \r\n");
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if (p1 != NULL && p2 != NULL && p3 != NULL && p4 != NULL) {
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CTypeRewriteStruct rewrite;
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rewrite.m_fromSlot = ::atoi(p1);
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rewrite.m_fromTG = ::atoi(p2);
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rewrite.m_toSlot = ::atoi(p3);
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rewrite.m_toId = ::atoi(p4);
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char* p5 = ::strtok(NULL, " \r\n");
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rewrite.m_range = p5 != NULL ? ::atoi(p5) : 1;
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m_dmrNetwork4TypeRewrites.push_back(rewrite);
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}
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} else if (::strncmp(key, "SrcRewrite", 10U) == 0) {
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@@ -861,13 +869,15 @@ bool CConf::read()
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char* p1 = ::strtok(value, ", ");
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char* p2 = ::strtok(NULL, ", ");
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char* p3 = ::strtok(NULL, ", ");
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char* p4 = ::strtok(NULL, " \r\n");
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char* p4 = ::strtok(NULL, ", \r\n");
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if (p1 != NULL && p2 != NULL && p3 != NULL && p4 != NULL) {
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CTypeRewriteStruct rewrite;
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rewrite.m_fromSlot = ::atoi(p1);
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rewrite.m_fromTG = ::atoi(p2);
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rewrite.m_toSlot = ::atoi(p3);
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rewrite.m_toId = ::atoi(p4);
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char* p5 = ::strtok(NULL, " \r\n");
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rewrite.m_range = p5 != NULL ? ::atoi(p5) : 1;
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m_dmrNetwork5TypeRewrites.push_back(rewrite);
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}
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} else if (::strncmp(key, "SrcRewrite", 10U) == 0) {
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1
Conf.h
1
Conf.h
@@ -43,6 +43,7 @@ struct CTypeRewriteStruct {
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unsigned int m_fromTG;
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unsigned int m_toSlot;
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unsigned int m_toId;
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unsigned int m_range;
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};
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struct CSrcRewriteStruct {
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@@ -1331,9 +1331,12 @@ bool CDMRGateway::createDMRNetwork1()
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std::vector<CTypeRewriteStruct> typeRewrites = m_conf.getDMRNetwork1TypeRewrites();
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for (std::vector<CTypeRewriteStruct>::const_iterator it = typeRewrites.begin(); it != typeRewrites.end(); ++it) {
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if ((*it).m_range == 1)
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LogInfo(" Rewrite RF: %u:TG%u -> %u:%u", (*it).m_fromSlot, (*it).m_fromTG, (*it).m_toSlot, (*it).m_toId);
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else
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LogInfo(" Rewrite RF: %u:TG%u-%u -> %u:%u-%u", (*it).m_fromSlot, (*it).m_fromTG, (*it).m_fromTG + (*it).m_range - 1U, (*it).m_toSlot, (*it).m_toId, (*it).m_toId + (*it).m_range - 1U);
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CRewriteType* rewrite = new CRewriteType(m_dmr1Name, (*it).m_fromSlot, (*it).m_fromTG, (*it).m_toSlot, (*it).m_toId);
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CRewriteType* rewrite = new CRewriteType(m_dmr1Name, (*it).m_fromSlot, (*it).m_fromTG, (*it).m_toSlot, (*it).m_toId, (*it).m_range);
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m_dmr1RFRewrites.push_back(rewrite);
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}
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@@ -1495,9 +1498,12 @@ bool CDMRGateway::createDMRNetwork2()
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std::vector<CTypeRewriteStruct> typeRewrites = m_conf.getDMRNetwork2TypeRewrites();
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for (std::vector<CTypeRewriteStruct>::const_iterator it = typeRewrites.begin(); it != typeRewrites.end(); ++it) {
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if ((*it).m_range == 1)
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LogInfo(" Rewrite RF: %u:TG%u -> %u:%u", (*it).m_fromSlot, (*it).m_fromTG, (*it).m_toSlot, (*it).m_toId);
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else
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LogInfo(" Rewrite RF: %u:TG%u-%u -> %u:%u-%u", (*it).m_fromSlot, (*it).m_fromTG, (*it).m_fromTG + (*it).m_range - 1U, (*it).m_toSlot, (*it).m_toId, (*it).m_toId + (*it).m_range - 1U);
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CRewriteType* rewrite = new CRewriteType(m_dmr2Name, (*it).m_fromSlot, (*it).m_fromTG, (*it).m_toSlot, (*it).m_toId);
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CRewriteType* rewrite = new CRewriteType(m_dmr2Name, (*it).m_fromSlot, (*it).m_fromTG, (*it).m_toSlot, (*it).m_toId, (*it).m_range);
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m_dmr2RFRewrites.push_back(rewrite);
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}
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@@ -1659,9 +1665,12 @@ bool CDMRGateway::createDMRNetwork3()
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std::vector<CTypeRewriteStruct> typeRewrites = m_conf.getDMRNetwork3TypeRewrites();
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for (std::vector<CTypeRewriteStruct>::const_iterator it = typeRewrites.begin(); it != typeRewrites.end(); ++it) {
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if ((*it).m_range == 1)
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LogInfo(" Rewrite RF: %u:TG%u -> %u:%u", (*it).m_fromSlot, (*it).m_fromTG, (*it).m_toSlot, (*it).m_toId);
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else
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LogInfo(" Rewrite RF: %u:TG%u-%u -> %u:%u-%u", (*it).m_fromSlot, (*it).m_fromTG, (*it).m_fromTG + (*it).m_range - 1U, (*it).m_toSlot, (*it).m_toId, (*it).m_toId + (*it).m_range - 1U);
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CRewriteType* rewrite = new CRewriteType(m_dmr3Name, (*it).m_fromSlot, (*it).m_fromTG, (*it).m_toSlot, (*it).m_toId);
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CRewriteType* rewrite = new CRewriteType(m_dmr3Name, (*it).m_fromSlot, (*it).m_fromTG, (*it).m_toSlot, (*it).m_toId, (*it).m_range);
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m_dmr3RFRewrites.push_back(rewrite);
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}
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@@ -1823,9 +1832,12 @@ bool CDMRGateway::createDMRNetwork4()
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std::vector<CTypeRewriteStruct> typeRewrites = m_conf.getDMRNetwork4TypeRewrites();
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for (std::vector<CTypeRewriteStruct>::const_iterator it = typeRewrites.begin(); it != typeRewrites.end(); ++it) {
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if ((*it).m_range == 1)
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LogInfo(" Rewrite RF: %u:TG%u -> %u:%u", (*it).m_fromSlot, (*it).m_fromTG, (*it).m_toSlot, (*it).m_toId);
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else
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LogInfo(" Rewrite RF: %u:TG%u-%u -> %u:%u-%u", (*it).m_fromSlot, (*it).m_fromTG, (*it).m_fromTG + (*it).m_range - 1U, (*it).m_toSlot, (*it).m_toId, (*it).m_toId + (*it).m_range - 1U);
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CRewriteType* rewrite = new CRewriteType(m_dmr4Name, (*it).m_fromSlot, (*it).m_fromTG, (*it).m_toSlot, (*it).m_toId);
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CRewriteType* rewrite = new CRewriteType(m_dmr4Name, (*it).m_fromSlot, (*it).m_fromTG, (*it).m_toSlot, (*it).m_toId, (*it).m_range);
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m_dmr4RFRewrites.push_back(rewrite);
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}
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@@ -1987,9 +1999,12 @@ bool CDMRGateway::createDMRNetwork5()
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std::vector<CTypeRewriteStruct> typeRewrites = m_conf.getDMRNetwork5TypeRewrites();
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for (std::vector<CTypeRewriteStruct>::const_iterator it = typeRewrites.begin(); it != typeRewrites.end(); ++it) {
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if ((*it).m_range == 1)
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LogInfo(" Rewrite RF: %u:TG%u -> %u:%u", (*it).m_fromSlot, (*it).m_fromTG, (*it).m_toSlot, (*it).m_toId);
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else
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LogInfo(" Rewrite RF: %u:TG%u-%u -> %u:%u-%u", (*it).m_fromSlot, (*it).m_fromTG, (*it).m_fromTG + (*it).m_range - 1U, (*it).m_toSlot, (*it).m_toId, (*it).m_toId + (*it).m_range - 1U);
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CRewriteType* rewrite = new CRewriteType(m_dmr5Name, (*it).m_fromSlot, (*it).m_fromTG, (*it).m_toSlot, (*it).m_toId);
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CRewriteType* rewrite = new CRewriteType(m_dmr5Name, (*it).m_fromSlot, (*it).m_fromTG, (*it).m_toSlot, (*it).m_toId, (*it).m_range);
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m_dmr5RFRewrites.push_back(rewrite);
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}
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@@ -24,13 +24,15 @@
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#include <cstdio>
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#include <cassert>
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CRewriteType::CRewriteType(const std::string& name, unsigned int fromSlot, unsigned int fromTG, unsigned int toSlot, unsigned int toId) :
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CRewriteType::CRewriteType(const std::string& name, unsigned int fromSlot, unsigned int fromTG, unsigned int toSlot, unsigned int toId, unsigned int range) :
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CRewrite(),
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m_name(name),
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m_fromSlot(fromSlot),
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m_fromTG(fromTG),
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m_fromTGStart(fromTG),
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m_fromTGEnd(fromTG + range - 1U),
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m_toSlot(toSlot),
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m_toId(toId)
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m_toIdStart(toId),
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m_toIdEnd(toId + range - 1U)
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{
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assert(fromSlot == 1U || fromSlot == 2U);
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assert(toSlot == 1U || toSlot == 2U);
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@@ -46,23 +48,37 @@ PROCESS_RESULT CRewriteType::process(CDMRData& data, bool trace)
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unsigned int dstId = data.getDstId();
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unsigned int slotNo = data.getSlotNo();
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if (flco != FLCO_GROUP || slotNo != m_fromSlot || dstId != m_fromTG) {
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if (trace)
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LogDebug("Rule Trace,\tRewriteType %s Slot=%u Dst=TG%u: not matched", m_name.c_str(), m_fromSlot, m_fromTG);
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if (flco != FLCO_GROUP || slotNo != m_fromSlot || dstId < m_fromTGStart || dstId > m_fromTGEnd) {
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if (trace) {
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if (m_fromTGStart == m_fromTGEnd)
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LogDebug("Rule Trace,\tRewriteType from \"%s\" Slot=%u Dst=TG%u: not matched", m_name.c_str(), m_fromSlot, m_fromTGStart);
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else
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LogDebug("Rule Trace,\tRewriteType from \"%s\" Slot=%u Dst=TG%u-%u: not matched", m_name.c_str(), m_fromSlot, m_fromTGStart, m_fromTGEnd);
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}
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return RESULT_UNMATCHED;
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}
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if (m_fromSlot != m_toSlot)
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data.setSlotNo(m_toSlot);
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data.setDstId(m_toId);
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if (m_fromTGStart != m_toIdStart) {
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unsigned int newDstId = dstId + m_toIdStart - m_fromTGStart;
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data.setDstId(newDstId);
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}
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data.setFLCO(FLCO_USER_USER);
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processMessage(data);
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if (trace)
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LogDebug("Rule Trace,\tRewriteType %s Slot=%u Dst=TG%u: matched", m_name.c_str(), m_fromSlot, m_fromTG);
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if (trace) {
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if (m_fromTGStart == m_fromTGEnd)
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LogDebug("Rule Trace,\tRewriteType from \"%s\" Slot=%u Dst=TG%u: not matched", m_name.c_str(), m_fromSlot, m_fromTGStart);
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else
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LogDebug("Rule Trace,\tRewriteType from \"%s\" Slot=%u Dst=TG%u-%u: not matched", m_name.c_str(), m_fromSlot, m_fromTGStart, m_fromTGEnd);
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if (m_toIdStart == m_toIdEnd)
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LogDebug("Rule Trace,\tRewriteType to \"\%s\" Slot=%u Dst=%u: matched", m_name.c_str(), m_toSlot, m_toIdStart);
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else
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LogDebug("Rule Trace,\tRewriteType to \"\%s\" Slot=%u Dst=%u-%u: matched", m_name.c_str(), m_toSlot, m_toIdStart, m_toIdEnd);
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}
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return RESULT_MATCHED;
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}
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@@ -26,7 +26,7 @@
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class CRewriteType : public CRewrite {
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public:
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CRewriteType(const std::string& name, unsigned int fromSlot, unsigned int fromTG, unsigned int toSlot, unsigned int toId);
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CRewriteType(const std::string& name, unsigned int fromSlot, unsigned int fromTG, unsigned int toSlot, unsigned int toId, unsigned int range);
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virtual ~CRewriteType();
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virtual PROCESS_RESULT process(CDMRData& data, bool trace);
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@@ -34,9 +34,11 @@ public:
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private:
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std::string m_name;
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unsigned int m_fromSlot;
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unsigned int m_fromTG;
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unsigned int m_fromTGStart;
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unsigned int m_fromTGEnd;
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unsigned int m_toSlot;
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unsigned int m_toId;
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unsigned int m_toIdStart;
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unsigned int m_toIdEnd;
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};
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