diff --git a/DMRGateway.cpp b/DMRGateway.cpp
index 3f035b7..9c16180 100644
--- a/DMRGateway.cpp
+++ b/DMRGateway.cpp
@@ -289,7 +289,6 @@ int CDMRGateway::run()
 	}
 
 	if (m_killed) {
-//		LogMessage("DMRGateway-%s is exiting on receipt of SIGHUP1", VERSION);
 		m_repeater->close();
 		delete m_repeater;
 		return 0;
@@ -301,13 +300,13 @@ int CDMRGateway::run()
 	LogInfo("Rule trace: %s", ruleTrace ? "yes" : "no");
 
 	if (m_conf.getDMRNetwork1Enabled()) {
-		ret = createDMRNetwork1(ruleTrace);
+		ret = createDMRNetwork1();
 		if (!ret)
 			return 1;
 	}
 
 	if (m_conf.getDMRNetwork2Enabled()) {
-		ret = createDMRNetwork2(ruleTrace);
+		ret = createDMRNetwork2();
 		if (!ret)
 			return 1;
 	}
@@ -431,12 +430,12 @@ int CDMRGateway::run()
 			FLCO flco = data.getFLCO();
 
 			if (flco == FLCO_GROUP && slotNo == m_xlx1Slot && dstId == m_xlx1TG) {
-				m_xlx1Rewrite->processRF(data);
+				m_xlx1Rewrite->process(data, false);
 				m_xlxNetwork1->write(data);
 				status[slotNo] = DMRGWS_XLXREFLECTOR1;
 				timer[slotNo]->start();
 			} else if (flco == FLCO_GROUP && slotNo == m_xlx2Slot && dstId == m_xlx2TG) {
-				m_xlx2Rewrite->processRF(data);
+				m_xlx2Rewrite->process(data, false);
 				m_xlxNetwork2->write(data);
 				status[slotNo] = DMRGWS_XLXREFLECTOR2;
 				timer[slotNo]->start();
@@ -536,7 +535,7 @@ int CDMRGateway::run()
 				if (m_dmrNetwork1 != NULL) {
 					// Rewrite the slot and/or TG or neither
 					for (std::vector<IRewrite*>::iterator it = m_dmr1RFRewrites.begin(); it != m_dmr1RFRewrites.end(); ++it) {
-						bool ret = (*it)->processRF(data);
+						bool ret = (*it)->process(data, ruleTrace);
 						if (ret) {
 							rewritten = true;
 							break;
@@ -556,7 +555,7 @@ int CDMRGateway::run()
 					if (m_dmrNetwork2 != NULL) {
 						// Rewrite the slot and/or TG or neither
 						for (std::vector<IRewrite*>::iterator it = m_dmr2RFRewrites.begin(); it != m_dmr2RFRewrites.end(); ++it) {
-							bool ret = (*it)->processRF(data);
+							bool ret = (*it)->process(data, ruleTrace);
 							if (ret) {
 								rewritten = true;
 								break;
@@ -576,7 +575,7 @@ int CDMRGateway::run()
 				if (!rewritten) {
 					if (m_dmrNetwork1 != NULL) {
 						for (std::vector<IRewrite*>::iterator it = m_dmr1Passalls.begin(); it != m_dmr1Passalls.end(); ++it) {
-							bool ret = (*it)->processRF(data);
+							bool ret = (*it)->process(data, ruleTrace);
 							if (ret) {
 								rewritten = true;
 								break;
@@ -596,7 +595,7 @@ int CDMRGateway::run()
 				if (!rewritten) {
 					if (m_dmrNetwork2 != NULL) {
 						for (std::vector<IRewrite*>::iterator it = m_dmr2Passalls.begin(); it != m_dmr2Passalls.end(); ++it) {
-							bool ret = (*it)->processRF(data);
+							bool ret = (*it)->process(data, ruleTrace);
 							if (ret) {
 								rewritten = true;
 								break;
@@ -622,7 +621,7 @@ int CDMRGateway::run()
 			ret = m_xlxNetwork1->read(data);
 			if (ret) {
 				if (status[m_xlx1Slot] == DMRGWS_NONE || status[m_xlx1Slot] == DMRGWS_XLXREFLECTOR1) {
-					bool ret = m_rpt1Rewrite->processNet(data);
+					bool ret = m_rpt1Rewrite->process(data, false);
 					if (ret) {
 						m_repeater->write(data);
 						status[m_xlx1Slot] = DMRGWS_XLXREFLECTOR1;
@@ -641,7 +640,7 @@ int CDMRGateway::run()
 			ret = m_xlxNetwork2->read(data);
 			if (ret) {
 				if (status[m_xlx2Slot] == DMRGWS_NONE || status[m_xlx2Slot] == DMRGWS_XLXREFLECTOR2) {
-					bool ret = m_rpt2Rewrite->processNet(data);
+					bool ret = m_rpt2Rewrite->process(data, false);
 					if (ret) {
 						m_repeater->write(data);
 						status[m_xlx2Slot] = DMRGWS_XLXREFLECTOR2;
@@ -671,7 +670,7 @@ int CDMRGateway::run()
 				// Rewrite the slot and/or TG or neither
 				bool rewritten = false;
 				for (std::vector<IRewrite*>::iterator it = m_dmr1NetRewrites.begin(); it != m_dmr1NetRewrites.end(); ++it) {
-					bool ret = (*it)->processNet(data);
+					bool ret = (*it)->process(data, ruleTrace);
 					if (ret) {
 						rewritten = true;
 						break;
@@ -709,7 +708,7 @@ int CDMRGateway::run()
 				// Rewrite the slot and/or TG or neither
 				bool rewritten = false;
 				for (std::vector<IRewrite*>::iterator it = m_dmr2NetRewrites.begin(); it != m_dmr2NetRewrites.end(); ++it) {
-					bool ret = (*it)->processNet(data);
+					bool ret = (*it)->process(data, ruleTrace);
 					if (ret) {
 						rewritten = true;
 						break;
@@ -869,7 +868,7 @@ bool CDMRGateway::createMMDVM()
 	return true;
 }
 
-bool CDMRGateway::createDMRNetwork1(bool trace)
+bool CDMRGateway::createDMRNetwork1()
 {
 	std::string address  = m_conf.getDMRNetwork1Address();
 	unsigned int port    = m_conf.getDMRNetwork1Port();
@@ -918,8 +917,8 @@ bool CDMRGateway::createDMRNetwork1(bool trace)
 		LogInfo("    Rewrite RF: %u:TG%u-TG%u -> %u:TG%u-TG%u", (*it).m_fromSlot, (*it).m_fromTG, (*it).m_fromTG + (*it).m_range - 1U, (*it).m_toSlot, (*it).m_toTG, (*it).m_toTG + (*it).m_range - 1U);
 		LogInfo("    Rewrite Net: %u:TG%u-TG%u -> %u:TG%u-TG%u", (*it).m_toSlot, (*it).m_toTG, (*it).m_toTG + (*it).m_range - 1U, (*it).m_fromSlot, (*it).m_fromTG, (*it).m_fromTG + (*it).m_range - 1U);
 
-		CRewriteTG* rfRewrite  = new CRewriteTG("DMR-1", (*it).m_fromSlot, (*it).m_fromTG, (*it).m_toSlot, (*it).m_toTG, (*it).m_range, trace);
-		CRewriteTG* netRewrite = new CRewriteTG("DMR-1", (*it).m_toSlot, (*it).m_toTG, (*it).m_fromSlot, (*it).m_fromTG, (*it).m_range, trace);
+		CRewriteTG* rfRewrite  = new CRewriteTG("DMR-1", (*it).m_fromSlot, (*it).m_fromTG, (*it).m_toSlot, (*it).m_toTG, (*it).m_range);
+		CRewriteTG* netRewrite = new CRewriteTG("DMR-1", (*it).m_toSlot, (*it).m_toTG, (*it).m_fromSlot, (*it).m_fromTG, (*it).m_range);
 
 		m_dmr1RFRewrites.push_back(rfRewrite);
 		m_dmr1NetRewrites.push_back(netRewrite);
@@ -929,7 +928,7 @@ bool CDMRGateway::createDMRNetwork1(bool trace)
 	for (std::vector<CPCRewriteStruct>::const_iterator it = pcRewrites.begin(); it != pcRewrites.end(); ++it) {
 		LogInfo("    Rewrite RF: %u:%u-%u -> %u:%u-%u", (*it).m_fromSlot, (*it).m_fromId, (*it).m_fromId + (*it).m_range - 1U, (*it).m_toSlot, (*it).m_toId, (*it).m_toId + (*it).m_range - 1U);
 
-		CRewritePC* rewrite = new CRewritePC("DMR-1", (*it).m_fromSlot, (*it).m_fromId, (*it).m_toSlot, (*it).m_toId, (*it).m_range, trace);
+		CRewritePC* rewrite = new CRewritePC("DMR-1", (*it).m_fromSlot, (*it).m_fromId, (*it).m_toSlot, (*it).m_toId, (*it).m_range);
 
 		m_dmr1RFRewrites.push_back(rewrite);
 	}
@@ -938,7 +937,7 @@ bool CDMRGateway::createDMRNetwork1(bool trace)
 	for (std::vector<CTypeRewriteStruct>::const_iterator it = typeRewrites.begin(); it != typeRewrites.end(); ++it) {
 		LogInfo("    Rewrite RF: %u:TG%u -> %u:%u", (*it).m_fromSlot, (*it).m_fromTG, (*it).m_toSlot, (*it).m_toId);
 
-		CRewriteType* rewrite = new CRewriteType("DMR-1", (*it).m_fromSlot, (*it).m_fromTG, (*it).m_toSlot, (*it).m_toId, trace);
+		CRewriteType* rewrite = new CRewriteType("DMR-1", (*it).m_fromSlot, (*it).m_fromTG, (*it).m_toSlot, (*it).m_toId);
 
 		m_dmr1RFRewrites.push_back(rewrite);
 	}
@@ -947,7 +946,7 @@ bool CDMRGateway::createDMRNetwork1(bool trace)
 	for (std::vector<CSrcRewriteStruct>::const_iterator it = srcRewrites.begin(); it != srcRewrites.end(); ++it) {
 		LogInfo("    Rewrite Net: %u:%u-%u -> %u:TG%u", (*it).m_fromSlot, (*it).m_fromId, (*it).m_fromId + (*it).m_range - 1U, (*it).m_toSlot, (*it).m_toTG);
 
-		CRewriteSrc* rewrite = new CRewriteSrc("DMR-1", (*it).m_fromSlot, (*it).m_fromId, (*it).m_toSlot, (*it).m_toTG, (*it).m_range, trace);
+		CRewriteSrc* rewrite = new CRewriteSrc("DMR-1", (*it).m_fromSlot, (*it).m_fromId, (*it).m_toSlot, (*it).m_toTG, (*it).m_range);
 
 		m_dmr1NetRewrites.push_back(rewrite);
 	}
@@ -956,8 +955,8 @@ bool CDMRGateway::createDMRNetwork1(bool trace)
 	for (std::vector<unsigned int>::const_iterator it = tgPassAll.begin(); it != tgPassAll.end(); ++it) {
 		LogInfo("    Pass All TG: %u", *it);
 
-		CPassAllTG* rfPassAllTG  = new CPassAllTG("DMR-1", *it, trace);
-		CPassAllTG* netPassAllTG = new CPassAllTG("DMR-1", *it, trace);
+		CPassAllTG* rfPassAllTG  = new CPassAllTG("DMR-1", *it);
+		CPassAllTG* netPassAllTG = new CPassAllTG("DMR-1", *it);
 
 		m_dmr1Passalls.push_back(rfPassAllTG);
 		m_dmr1NetRewrites.push_back(netPassAllTG);
@@ -967,8 +966,8 @@ bool CDMRGateway::createDMRNetwork1(bool trace)
 	for (std::vector<unsigned int>::const_iterator it = pcPassAll.begin(); it != pcPassAll.end(); ++it) {
 		LogInfo("    Pass All PC: %u", *it);
 
-		CPassAllPC* rfPassAllPC  = new CPassAllPC("DMR-1", *it, trace);
-		CPassAllPC* netPassAllPC = new CPassAllPC("DMR-1", *it, trace);
+		CPassAllPC* rfPassAllPC  = new CPassAllPC("DMR-1", *it);
+		CPassAllPC* netPassAllPC = new CPassAllPC("DMR-1", *it);
 
 		m_dmr1Passalls.push_back(rfPassAllPC);
 		m_dmr1NetRewrites.push_back(netPassAllPC);
@@ -977,7 +976,7 @@ bool CDMRGateway::createDMRNetwork1(bool trace)
 	return true;
 }
 
-bool CDMRGateway::createDMRNetwork2(bool trace)
+bool CDMRGateway::createDMRNetwork2()
 {
 	std::string address  = m_conf.getDMRNetwork2Address();
 	unsigned int port    = m_conf.getDMRNetwork2Port();
@@ -1026,8 +1025,8 @@ bool CDMRGateway::createDMRNetwork2(bool trace)
 		LogInfo("    Rewrite RF: %u:TG%u-TG%u -> %u:TG%u-TG%u", (*it).m_fromSlot, (*it).m_fromTG, (*it).m_fromTG + (*it).m_range - 1U, (*it).m_toSlot, (*it).m_toTG, (*it).m_toTG + (*it).m_range - 1U);
 		LogInfo("    Rewrite Net: %u:TG%u-TG%u -> %u:TG%u-TG%u", (*it).m_toSlot, (*it).m_toTG, (*it).m_toTG + (*it).m_range - 1U, (*it).m_fromSlot, (*it).m_fromTG, (*it).m_fromTG + (*it).m_range - 1U);
 
-		CRewriteTG* rfRewrite  = new CRewriteTG("DMR-2", (*it).m_fromSlot, (*it).m_fromTG, (*it).m_toSlot, (*it).m_toTG, (*it).m_range, trace);
-		CRewriteTG* netRewrite = new CRewriteTG("DMR-2", (*it).m_toSlot, (*it).m_toTG, (*it).m_fromSlot, (*it).m_fromTG, (*it).m_range, trace);
+		CRewriteTG* rfRewrite  = new CRewriteTG("DMR-2", (*it).m_fromSlot, (*it).m_fromTG, (*it).m_toSlot, (*it).m_toTG, (*it).m_range);
+		CRewriteTG* netRewrite = new CRewriteTG("DMR-2", (*it).m_toSlot, (*it).m_toTG, (*it).m_fromSlot, (*it).m_fromTG, (*it).m_range);
 
 		m_dmr2RFRewrites.push_back(rfRewrite);
 		m_dmr2NetRewrites.push_back(netRewrite);
@@ -1037,7 +1036,7 @@ bool CDMRGateway::createDMRNetwork2(bool trace)
 	for (std::vector<CPCRewriteStruct>::const_iterator it = pcRewrites.begin(); it != pcRewrites.end(); ++it) {
 		LogInfo("    Rewrite RF: %u:%u-%u -> %u:%u-%u", (*it).m_fromSlot, (*it).m_fromId, (*it).m_fromId + (*it).m_range - 1U, (*it).m_toSlot, (*it).m_toId, (*it).m_toId + (*it).m_range - 1U);
 
-		CRewritePC* rewrite = new CRewritePC("DMR-2", (*it).m_fromSlot, (*it).m_fromId, (*it).m_toSlot, (*it).m_toId, (*it).m_range, trace);
+		CRewritePC* rewrite = new CRewritePC("DMR-2", (*it).m_fromSlot, (*it).m_fromId, (*it).m_toSlot, (*it).m_toId, (*it).m_range);
 
 		m_dmr2RFRewrites.push_back(rewrite);
 	}
@@ -1046,7 +1045,7 @@ bool CDMRGateway::createDMRNetwork2(bool trace)
 	for (std::vector<CTypeRewriteStruct>::const_iterator it = typeRewrites.begin(); it != typeRewrites.end(); ++it) {
 		LogInfo("    Rewrite RF: %u:TG%u -> %u:%u", (*it).m_fromSlot, (*it).m_fromTG, (*it).m_toSlot, (*it).m_toId);
 
-		CRewriteType* rewrite = new CRewriteType("DMR-2", (*it).m_fromSlot, (*it).m_fromTG, (*it).m_toSlot, (*it).m_toId, trace);
+		CRewriteType* rewrite = new CRewriteType("DMR-2", (*it).m_fromSlot, (*it).m_fromTG, (*it).m_toSlot, (*it).m_toId);
 
 		m_dmr2RFRewrites.push_back(rewrite);
 	}
@@ -1055,7 +1054,7 @@ bool CDMRGateway::createDMRNetwork2(bool trace)
 	for (std::vector<CSrcRewriteStruct>::const_iterator it = srcRewrites.begin(); it != srcRewrites.end(); ++it) {
 		LogInfo("    Rewrite Net: %u:%u-%u -> %u:TG%u", (*it).m_fromSlot, (*it).m_fromId, (*it).m_fromId + (*it).m_range - 1U, (*it).m_toSlot, (*it).m_toTG);
 
-		CRewriteSrc* rewrite = new CRewriteSrc("DMR-2", (*it).m_fromSlot, (*it).m_fromId, (*it).m_toSlot, (*it).m_toTG, (*it).m_range, trace);
+		CRewriteSrc* rewrite = new CRewriteSrc("DMR-2", (*it).m_fromSlot, (*it).m_fromId, (*it).m_toSlot, (*it).m_toTG, (*it).m_range);
 
 		m_dmr2NetRewrites.push_back(rewrite);
 	}
@@ -1064,8 +1063,8 @@ bool CDMRGateway::createDMRNetwork2(bool trace)
 	for (std::vector<unsigned int>::const_iterator it = tgPassAll.begin(); it != tgPassAll.end(); ++it) {
 		LogInfo("    Pass All TG: %u", *it);
 
-		CPassAllTG* rfPassAllTG  = new CPassAllTG("DMR-2", *it, trace);
-		CPassAllTG* netPassAllTG = new CPassAllTG("DMR-2", *it, trace);
+		CPassAllTG* rfPassAllTG  = new CPassAllTG("DMR-2", *it);
+		CPassAllTG* netPassAllTG = new CPassAllTG("DMR-2", *it);
 
 		m_dmr2Passalls.push_back(rfPassAllTG);
 		m_dmr2NetRewrites.push_back(netPassAllTG);
@@ -1075,8 +1074,8 @@ bool CDMRGateway::createDMRNetwork2(bool trace)
 	for (std::vector<unsigned int>::const_iterator it = pcPassAll.begin(); it != pcPassAll.end(); ++it) {
 		LogInfo("    Pass All PC: %u", *it);
 
-		CPassAllPC* rfPassAllPC  = new CPassAllPC("DMR-2", *it, trace);
-		CPassAllPC* netPassAllPC = new CPassAllPC("DMR-2", *it, trace);
+		CPassAllPC* rfPassAllPC  = new CPassAllPC("DMR-2", *it);
+		CPassAllPC* netPassAllPC = new CPassAllPC("DMR-2", *it);
 
 		m_dmr2Passalls.push_back(rfPassAllPC);
 		m_dmr2NetRewrites.push_back(netPassAllPC);
@@ -1137,8 +1136,8 @@ bool CDMRGateway::createXLXNetwork1()
 	if (m_xlx1Startup != 4000U)
 		LogInfo("    Startup: %u", m_xlx1Startup);
 
-	m_rpt1Rewrite = new CRewriteTG("XLX-1", XLX_SLOT, XLX_TG, m_xlx1Slot, m_xlx1TG, 1U, false);
-	m_xlx1Rewrite = new CRewriteTG("XLX-1", m_xlx1Slot, m_xlx1TG, XLX_SLOT, XLX_TG, 1U, false);
+	m_rpt1Rewrite = new CRewriteTG("XLX-1", XLX_SLOT, XLX_TG, m_xlx1Slot, m_xlx1TG, 1U);
+	m_xlx1Rewrite = new CRewriteTG("XLX-1", m_xlx1Slot, m_xlx1TG, XLX_SLOT, XLX_TG, 1U);
 
 	return true;
 }
@@ -1195,8 +1194,8 @@ bool CDMRGateway::createXLXNetwork2()
 	if (m_xlx2Startup != 4000U)
 		LogInfo("    Startup: %u", m_xlx2Startup);
 
-	m_rpt2Rewrite = new CRewriteTG("XLX-2", XLX_SLOT, XLX_TG, m_xlx2Slot, m_xlx2TG, 1U, false);
-	m_xlx2Rewrite = new CRewriteTG("XLX-2", m_xlx2Slot, m_xlx2TG, XLX_SLOT, XLX_TG, 1U, false);
+	m_rpt2Rewrite = new CRewriteTG("XLX-2", XLX_SLOT, XLX_TG, m_xlx2Slot, m_xlx2TG, 1U);
+	m_xlx2Rewrite = new CRewriteTG("XLX-2", m_xlx2Slot, m_xlx2TG, XLX_SLOT, XLX_TG, 1U);
 
 	return true;
 }
diff --git a/DMRGateway.h b/DMRGateway.h
index fa35507..345ac5d 100644
--- a/DMRGateway.h
+++ b/DMRGateway.h
@@ -69,8 +69,8 @@ private:
 	std::vector<IRewrite*> m_dmr2Passalls;
 
 	bool createMMDVM();
-	bool createDMRNetwork1(bool trace);
-	bool createDMRNetwork2(bool trace);
+	bool createDMRNetwork1();
+	bool createDMRNetwork2();
 	bool createXLXNetwork1();
 	bool createXLXNetwork2();
 	void writeXLXLink(unsigned int srcId, unsigned int dstId, CDMRNetwork* network);
diff --git a/PassAllPC.cpp b/PassAllPC.cpp
index 8852efb..edf5f50 100644
--- a/PassAllPC.cpp
+++ b/PassAllPC.cpp
@@ -24,10 +24,9 @@
 #include <cstdio>
 #include <cassert>
 
-CPassAllPC::CPassAllPC(const char* name, unsigned int slot, bool trace) :
+CPassAllPC::CPassAllPC(const char* name, unsigned int slot) :
 m_name(name),
-m_slot(slot),
-m_trace(trace)
+m_slot(slot)
 {
 	assert(slot == 1U || slot == 2U);
 }
@@ -36,30 +35,15 @@ CPassAllPC::~CPassAllPC()
 {
 }
 
-bool CPassAllPC::processRF(CDMRData& data)
-{
-	bool ret = process(data);
-
-	if (m_trace)
-		LogDebug("Rule Trace,\tPassAllPC %s Slot=%u: %s", m_name, m_slot, ret ? "matched" : "not matched");
-
-	return ret;
-}
-
-bool CPassAllPC::processNet(CDMRData& data)
-{
-	bool ret = process(data);
-
-	if (m_trace)
-		LogDebug("Rule Trace,\tPassAllPC %s Slot=%u: %s", m_name, m_slot, ret ? "matched" : "not matched");
-
-	return ret;
-}
-
-bool CPassAllPC::process(CDMRData& data)
+bool CPassAllPC::process(CDMRData& data, bool trace)
 {
 	FLCO flco = data.getFLCO();
 	unsigned int slotNo = data.getSlotNo();
 
-	return flco == FLCO_USER_USER && slotNo == m_slot;
+	bool ret = (flco == FLCO_USER_USER && slotNo == m_slot);
+
+	if (trace)
+		LogDebug("Rule Trace,\tPassAllPC %s Slot=%u: %s", m_name, m_slot, ret ? "matched" : "not matched");
+
+	return ret;
 }
diff --git a/PassAllPC.h b/PassAllPC.h
index cee8729..108d981 100644
--- a/PassAllPC.h
+++ b/PassAllPC.h
@@ -24,18 +24,14 @@
 
 class CPassAllPC : public IRewrite {
 public:
-	CPassAllPC(const char* name, unsigned int slot, bool trace);
+	CPassAllPC(const char* name, unsigned int slot);
 	virtual ~CPassAllPC();
 
-	virtual bool processRF(CDMRData& data);
-	virtual bool processNet(CDMRData& data);
+	virtual bool process(CDMRData& data, bool trace);
 
 private:
 	const char*  m_name;
 	unsigned int m_slot;
-	bool         m_trace;
-
-	bool process(CDMRData& data);
 };
 
 
diff --git a/PassAllTG.cpp b/PassAllTG.cpp
index a11697d..90f7ce5 100644
--- a/PassAllTG.cpp
+++ b/PassAllTG.cpp
@@ -24,10 +24,9 @@
 #include <cstdio>
 #include <cassert>
 
-CPassAllTG::CPassAllTG(const char* name, unsigned int slot, bool trace) :
+CPassAllTG::CPassAllTG(const char* name, unsigned int slot) :
 m_name(name),
-m_slot(slot),
-m_trace(trace)
+m_slot(slot)
 {
 	assert(slot == 1U || slot == 2U);
 }
@@ -36,30 +35,15 @@ CPassAllTG::~CPassAllTG()
 {
 }
 
-bool CPassAllTG::processRF(CDMRData& data)
-{
-	bool ret = process(data);
-
-	if (m_trace)
-		LogDebug("Rule Trace,\tPassAllTG %s Slot=%u: %s", m_name, m_slot, ret ? "matched" : "not matched");
-
-	return ret;
-}
-
-bool CPassAllTG::processNet(CDMRData& data)
-{
-	bool ret = process(data);
-
-	if (m_trace)
-		LogDebug("Rule Trace,\tPassAllTG %s Slot=%u: %s", m_name, m_slot, ret ? "matched" : "not matched");
-
-	return ret;
-}
-
-bool CPassAllTG::process(CDMRData& data)
+bool CPassAllTG::process(CDMRData& data, bool trace)
 {
 	FLCO flco = data.getFLCO();
 	unsigned int slotNo = data.getSlotNo();
 
-	return flco == FLCO_GROUP && slotNo == m_slot;
+	bool ret = (flco == FLCO_GROUP && slotNo == m_slot);
+
+	if (trace)
+		LogDebug("Rule Trace,\tPassAllTG %s Slot=%u: %s", m_name, m_slot, ret ? "matched" : "not matched");
+
+	return ret;
 }
diff --git a/PassAllTG.h b/PassAllTG.h
index 9780d61..032eec4 100644
--- a/PassAllTG.h
+++ b/PassAllTG.h
@@ -24,18 +24,14 @@
 
 class CPassAllTG : public IRewrite {
 public:
-	CPassAllTG(const char* name, unsigned int slot, bool trace);
+	CPassAllTG(const char* name, unsigned int slot);
 	virtual ~CPassAllTG();
 
-	virtual bool processRF(CDMRData& data);
-	virtual bool processNet(CDMRData& data);
+	virtual bool process(CDMRData& data, bool trace);
 
 private:
 	const char*  m_name;
 	unsigned int m_slot;
-	bool         m_trace;
-
-	bool process(CDMRData& data);
 };
 
 
diff --git a/Rewrite.h b/Rewrite.h
index c33723c..0292d10 100644
--- a/Rewrite.h
+++ b/Rewrite.h
@@ -25,8 +25,7 @@ class IRewrite {
 public:
 	virtual ~IRewrite() = 0;
 
-	virtual bool processRF(CDMRData& data) = 0;
-	virtual bool processNet(CDMRData& data) = 0;
+	virtual bool process(CDMRData& data, bool trace) = 0;
 
 private:
 };
diff --git a/RewritePC.cpp b/RewritePC.cpp
index 2f76aea..55c1367 100644
--- a/RewritePC.cpp
+++ b/RewritePC.cpp
@@ -25,7 +25,7 @@
 #include <cstdio>
 #include <cassert>
 
-CRewritePC::CRewritePC(const char* name, unsigned int fromSlot, unsigned int fromId, unsigned int toSlot, unsigned int toId, unsigned int range, bool trace) :
+CRewritePC::CRewritePC(const char* name, unsigned int fromSlot, unsigned int fromId, unsigned int toSlot, unsigned int toId, unsigned int range) :
 m_name(name),
 m_fromSlot(fromSlot),
 m_fromIdStart(fromId),
@@ -33,7 +33,6 @@ m_fromIdEnd(fromId + range - 1U),
 m_toSlot(toSlot),
 m_toIdStart(toId),
 m_toIdEnd(toId + range - 1U),
-m_trace(trace),
 m_lc(FLCO_USER_USER, 0U, 0U),
 m_embeddedLC()
 {
@@ -45,40 +44,17 @@ CRewritePC::~CRewritePC()
 {
 }
 
-bool CRewritePC::processRF(CDMRData& data)
-{
-	bool ret = process(data);
-
-	if (m_trace)
-		LogDebug("Rule Trace,\tRewritePC from %s Slot=%u Dst=%u-%u: %s", m_name, m_fromSlot, m_fromIdStart, m_fromIdEnd, ret ? "matched" : "not matched");
-		
-	if (m_trace && ret) 
-		LogDebug("Rule Trace,\tRewritePC to %s Slot=%u Dst=%u-%u", m_name, m_toSlot, m_toIdStart, m_toIdEnd);
-
-	return ret;
-}
-
-bool CRewritePC::processNet(CDMRData& data)
-{
-	bool ret = process(data);
-
-	if (m_trace)
-		LogDebug("Rule Trace,\tRewritePC from %s Slot=%u Dst=%u-%u: %s", m_name, m_fromSlot, m_fromIdStart, m_fromIdEnd, ret ? "matched" : "not matched");
-		
-	if (m_trace && ret) 
-		LogDebug("Rule Trace,\tRewritePC to %s Slot=%u Dst=%u-%u", m_name, m_toSlot, m_toIdStart, m_toIdEnd);
-
-	return ret;
-}
-
-bool CRewritePC::process(CDMRData& data)
+bool CRewritePC::process(CDMRData& data, bool trace)
 {
 	FLCO flco = data.getFLCO();
 	unsigned int dstId = data.getDstId();
 	unsigned int slotNo = data.getSlotNo();
 
-	if (flco != FLCO_USER_USER || slotNo != m_fromSlot || dstId < m_fromIdStart || dstId > m_fromIdEnd)
+	if (flco != FLCO_USER_USER || slotNo != m_fromSlot || dstId < m_fromIdStart || dstId > m_fromIdEnd) {
+		if (trace)
+			LogDebug("Rule Trace,\tRewritePC from %s Slot=%u Dst=%u-%u: not matched", m_name, m_fromSlot, m_fromIdStart, m_fromIdEnd);
 		return false;
+	}
 
 	if (m_fromSlot != m_toSlot)
 		data.setSlotNo(m_toSlot);
@@ -107,6 +83,11 @@ bool CRewritePC::process(CDMRData& data)
 		}
 	}
 
+	if (trace) {
+		LogDebug("Rule Trace,\tRewritePC from %s Slot=%u Dst=%u-%u: not matched", m_name, m_fromSlot, m_fromIdStart, m_fromIdEnd);
+		LogDebug("Rule Trace,\tRewritePC to %s Slot=%u Dst=%u-%u", m_name, m_toSlot, m_toIdStart, m_toIdEnd);
+	}
+
 	return true;
 }
 
diff --git a/RewritePC.h b/RewritePC.h
index 0379a12..9486a90 100644
--- a/RewritePC.h
+++ b/RewritePC.h
@@ -26,11 +26,10 @@
 
 class CRewritePC : public IRewrite {
 public:
-	CRewritePC(const char* name, unsigned int fromSlot, unsigned int fromId, unsigned int toSlot, unsigned int toId, unsigned int range, bool trace);
+	CRewritePC(const char* name, unsigned int fromSlot, unsigned int fromId, unsigned int toSlot, unsigned int toId, unsigned int range);
 	virtual ~CRewritePC();
 
-	virtual bool processRF(CDMRData& data);
-	virtual bool processNet(CDMRData& data);
+	virtual bool process(CDMRData& data, bool trace);
 
 private:
 	const char*      m_name;
@@ -40,11 +39,9 @@ private:
 	unsigned int     m_toSlot;
 	unsigned int     m_toIdStart;
 	unsigned int     m_toIdEnd;
-	bool             m_trace;
 	CDMRLC           m_lc;
 	CDMREmbeddedData m_embeddedLC;
 
-	bool process(CDMRData& data);
 	void processHeader(CDMRData& data, unsigned int dstId, unsigned char dataType);
 	void processVoice(CDMRData& data, unsigned int dstId);
 };
diff --git a/RewriteSrc.cpp b/RewriteSrc.cpp
index e9c8f3e..1b3e890 100644
--- a/RewriteSrc.cpp
+++ b/RewriteSrc.cpp
@@ -25,14 +25,13 @@
 #include <cstdio>
 #include <cassert>
 
-CRewriteSrc::CRewriteSrc(const char* name, unsigned int fromSlot, unsigned int fromId, unsigned int toSlot, unsigned int toTG, unsigned int range, bool trace) :
+CRewriteSrc::CRewriteSrc(const char* name, unsigned int fromSlot, unsigned int fromId, unsigned int toSlot, unsigned int toTG, unsigned int range) :
 m_name(name),
 m_fromSlot(fromSlot),
 m_fromIdStart(fromId),
 m_fromIdEnd(fromId + range - 1U),
 m_toSlot(toSlot),
 m_toTG(toTG),
-m_trace(trace),
 m_lc(FLCO_GROUP, 0U, toTG),
 m_embeddedLC()
 {
@@ -46,40 +45,17 @@ CRewriteSrc::~CRewriteSrc()
 {
 }
 
-bool CRewriteSrc::processRF(CDMRData& data)
-{
-	bool ret = process(data);
-
-	if (m_trace)
-		LogDebug("Rule Trace,\tRewriteSrc from %s Slot=%u Src=%u-%u: %s", m_name, m_fromSlot, m_fromIdStart, m_fromIdEnd, ret ? "matched" : "not matched");
-		
-	if (m_trace && ret) 
-		LogDebug("Rule Trace,\tRewriteSrc to %s Slot=%u Dst=TG%u", m_name, m_toSlot, m_toTG);
-
-	return ret;
-}
-
-bool CRewriteSrc::processNet(CDMRData& data)
-{
-	bool ret = process(data);
-
-	if (m_trace)
-		LogDebug("Rule Trace,\tRewriteSrc from %s Slot=%u Src=%u-%u: %s", m_name, m_fromSlot, m_fromIdStart, m_fromIdEnd, ret ? "matched" : "not matched");
-		
-	if (m_trace && ret) 
-		LogDebug("Rule Trace,\tRewriteSrc to %s Slot=%u Dst=TG%u", m_name, m_toSlot, m_toTG);
-
-	return ret;
-}
-
-bool CRewriteSrc::process(CDMRData& data)
+bool CRewriteSrc::process(CDMRData& data, bool trace)
 {
 	FLCO flco = data.getFLCO();
 	unsigned int srcId = data.getSrcId();
 	unsigned int slotNo = data.getSlotNo();
 
-	if (flco != FLCO_USER_USER || slotNo != m_fromSlot || srcId < m_fromIdStart || srcId > m_fromIdEnd)
+	if (flco != FLCO_USER_USER || slotNo != m_fromSlot || srcId < m_fromIdStart || srcId > m_fromIdEnd) {
+		if (trace)
+			LogDebug("Rule Trace,\tRewriteSrc from %s Slot=%u Src=%u-%u: not matched", m_name, m_fromSlot, m_fromIdStart, m_fromIdEnd);
 		return false;
+	}
 
 	if (m_fromSlot != m_toSlot)
 		data.setSlotNo(m_toSlot);
@@ -105,6 +81,11 @@ bool CRewriteSrc::process(CDMRData& data)
 		break;
 	}
 
+	if (trace) {
+		LogDebug("Rule Trace,\tRewriteSrc from %s Slot=%u Src=%u-%u: matched", m_name, m_fromSlot, m_fromIdStart, m_fromIdEnd);
+		LogDebug("Rule Trace,\tRewriteSrc to %s Slot=%u Dst=TG%u", m_name, m_toSlot, m_toTG);
+	}
+
 	return true;
 }
 
diff --git a/RewriteSrc.h b/RewriteSrc.h
index 3bc2325..ff323bb 100644
--- a/RewriteSrc.h
+++ b/RewriteSrc.h
@@ -26,11 +26,10 @@
 
 class CRewriteSrc : public IRewrite {
 public:
-	CRewriteSrc(const char* name, unsigned int fromSlot, unsigned int fromId, unsigned int toSlot, unsigned int toTG, unsigned int range, bool trace);
+	CRewriteSrc(const char* name, unsigned int fromSlot, unsigned int fromId, unsigned int toSlot, unsigned int toTG, unsigned int range);
 	virtual ~CRewriteSrc();
 
-	virtual bool processRF(CDMRData& data);
-	virtual bool processNet(CDMRData& data);
+	virtual bool process(CDMRData& data, bool trace);
 
 private:
 	const char*      m_name;
@@ -39,11 +38,9 @@ private:
 	unsigned int     m_fromIdEnd;
 	unsigned int     m_toSlot;
 	unsigned int     m_toTG;
-	bool             m_trace;
 	CDMRLC           m_lc;
 	CDMREmbeddedData m_embeddedLC;
 
-	bool process(CDMRData& data);
 	void processHeader(CDMRData& data, unsigned char dataType);
 	void processVoice(CDMRData& data);
 };
diff --git a/RewriteTG.cpp b/RewriteTG.cpp
index 63e3693..0ce9be4 100644
--- a/RewriteTG.cpp
+++ b/RewriteTG.cpp
@@ -25,7 +25,7 @@
 #include <cstdio>
 #include <cassert>
 
-CRewriteTG::CRewriteTG(const char* name, unsigned int fromSlot, unsigned int fromTG, unsigned int toSlot, unsigned int toTG, unsigned int range, bool trace) :
+CRewriteTG::CRewriteTG(const char* name, unsigned int fromSlot, unsigned int fromTG, unsigned int toSlot, unsigned int toTG, unsigned int range) :
 m_name(name),
 m_fromSlot(fromSlot),
 m_fromTGStart(fromTG),
@@ -33,7 +33,6 @@ m_fromTGEnd(fromTG + range - 1U),
 m_toSlot(toSlot),
 m_toTGStart(toTG),
 m_toTGEnd(toTG + range - 1U),
-m_trace(trace),
 m_lc(FLCO_GROUP, 0U, toTG),
 m_embeddedLC()
 {
@@ -45,40 +44,17 @@ CRewriteTG::~CRewriteTG()
 {
 }
 
-bool CRewriteTG::processRF(CDMRData& data)
+bool CRewriteTG::process(CDMRData& data, bool trace)
 {
-	bool ret = process(data);
-
-	if (m_trace)
-		LogDebug("Rule Trace,\tRewriteTG from %s Slot=%u Dst=TG%u-TG%u: %s", m_name, m_fromSlot, m_fromTGStart, m_fromTGEnd, ret ? "matched" : "not matched");
-		
-	if (m_trace && ret) 
-		LogDebug("Rule Trace,\tRewriteTG to %s Slot=%u Dst=TG%u-TG%u", m_name, m_toSlot, m_toTGStart, m_toTGEnd);
-
-	return ret;
-}
-
-bool CRewriteTG::processNet(CDMRData& data)
-{
-	bool ret = process(data);
-
-	if (m_trace)
-		LogDebug("Rule Trace,\tRewriteTG from %s Slot=%u Dst=TG%u-TG%u: %s", m_name, m_fromSlot, m_fromTGStart, m_fromTGEnd, ret ? "matched" : "not matched");
-		
-	if (m_trace && ret) 
-		LogDebug("Rule Trace,\tRewriteTG to %s Slot=%u Dst=TG%u-TG%u", m_name, m_toSlot, m_toTGStart, m_toTGEnd);
-
-	return ret;
-}
-
-bool CRewriteTG::process(CDMRData& data)
-{
-	FLCO flco           = data.getFLCO();
-	unsigned int dstId  = data.getDstId();
+	FLCO flco = data.getFLCO();
+	unsigned int dstId = data.getDstId();
 	unsigned int slotNo = data.getSlotNo();
 
-	if (flco != FLCO_GROUP || slotNo != m_fromSlot || dstId < m_fromTGStart || dstId > m_fromTGEnd)
+	if (flco != FLCO_GROUP || slotNo != m_fromSlot || dstId < m_fromTGStart || dstId > m_fromTGEnd) {
+		if (trace)
+			LogDebug("Rule Trace,\tRewriteTG from %s Slot=%u Dst=TG%u-TG%u: not matched", m_name, m_fromSlot, m_fromTGStart, m_fromTGEnd);
 		return false;
+	}
 
 	if (m_fromSlot != m_toSlot)
 		data.setSlotNo(m_toSlot);
@@ -107,6 +83,11 @@ bool CRewriteTG::process(CDMRData& data)
 		}
 	}
 
+	if (trace) {
+		LogDebug("Rule Trace,\tRewriteTG from %s Slot=%u Dst=TG%u-TG%u: matched", m_name, m_fromSlot, m_fromTGStart, m_fromTGEnd);
+		LogDebug("Rule Trace,\tRewriteTG to %s Slot=%u Dst=TG%u-TG%u", m_name, m_toSlot, m_toTGStart, m_toTGEnd);
+	}
+
 	return true;
 }
 
diff --git a/RewriteTG.h b/RewriteTG.h
index 3db2266..26d2f7d 100644
--- a/RewriteTG.h
+++ b/RewriteTG.h
@@ -26,11 +26,10 @@
 
 class CRewriteTG : public IRewrite {
 public:
-	CRewriteTG(const char*name, unsigned int fromSlot, unsigned int fromTG, unsigned int toSlot, unsigned int toTG, unsigned int range, bool trace);
+	CRewriteTG(const char*name, unsigned int fromSlot, unsigned int fromTG, unsigned int toSlot, unsigned int toTG, unsigned int range);
 	virtual ~CRewriteTG();
 
-	virtual bool processRF(CDMRData& data);
-	virtual bool processNet(CDMRData& data);
+	virtual bool process(CDMRData& data, bool trace);
 
 private:
 	const char*      m_name;
@@ -40,11 +39,9 @@ private:
 	unsigned int     m_toSlot;
 	unsigned int     m_toTGStart;
 	unsigned int     m_toTGEnd;
-	bool             m_trace;
 	CDMRLC           m_lc;
 	CDMREmbeddedData m_embeddedLC;
 
-	bool process(CDMRData& data);
 	void processHeader(CDMRData& data, unsigned int tg, unsigned char dataType);
 	void processVoice(CDMRData& data, unsigned int tg);
 };
diff --git a/RewriteType.cpp b/RewriteType.cpp
index 6f277cf..a4c0b39 100644
--- a/RewriteType.cpp
+++ b/RewriteType.cpp
@@ -25,13 +25,12 @@
 #include <cstdio>
 #include <cassert>
 
-CRewriteType::CRewriteType(const char* name, unsigned int fromSlot, unsigned int fromTG, unsigned int toSlot, unsigned int toId, bool trace) :
+CRewriteType::CRewriteType(const char* name, unsigned int fromSlot, unsigned int fromTG, unsigned int toSlot, unsigned int toId) :
 m_name(name),
 m_fromSlot(fromSlot),
 m_fromTG(fromTG),
 m_toSlot(toSlot),
 m_toId(toId),
-m_trace(trace),
 m_lc(FLCO_USER_USER, 0U, toId),
 m_embeddedLC()
 {
@@ -43,34 +42,17 @@ CRewriteType::~CRewriteType()
 {
 }
 
-bool CRewriteType::processRF(CDMRData& data)
-{
-	bool ret = process(data);
-
-	if (m_trace)
-		LogDebug("Rule Trace,\tRewriteType %s Slot=%u Dst=TG%u: %s", m_name, m_fromSlot, m_fromTG, ret ? "matched" : "not matched");
-
-	return ret;
-}
-
-bool CRewriteType::processNet(CDMRData& data)
-{
-	bool ret = process(data);
-
-	if (m_trace)
-		LogDebug("Rule Trace,\tRewriteType %s Slot=%u Dst=TG%u: %s", m_name, m_fromSlot, m_fromTG, ret ? "matched" : "not matched");
-
-	return ret;
-}
-
-bool CRewriteType::process(CDMRData& data)
+bool CRewriteType::process(CDMRData& data, bool trace)
 {
 	FLCO flco           = data.getFLCO();
 	unsigned int dstId  = data.getDstId();
 	unsigned int slotNo = data.getSlotNo();
 
-	if (flco != FLCO_GROUP || slotNo != m_fromSlot || dstId != m_fromTG)
+	if (flco != FLCO_GROUP || slotNo != m_fromSlot || dstId != m_fromTG) {
+		if (trace)
+			LogDebug("Rule Trace,\tRewriteType %s Slot=%u Dst=TG%u: not matched", m_name, m_fromSlot, m_fromTG);
 		return false;
+	}
 
 	if (m_fromSlot != m_toSlot)
 		data.setSlotNo(m_toSlot);
@@ -96,6 +78,9 @@ bool CRewriteType::process(CDMRData& data)
 		break;
 	}
 
+	if (trace)
+		LogDebug("Rule Trace,\tRewriteType %s Slot=%u Dst=TG%u: matched", m_name, m_fromSlot, m_fromTG);
+
 	return true;
 }
 
diff --git a/RewriteType.h b/RewriteType.h
index ccac537..30e4d53 100644
--- a/RewriteType.h
+++ b/RewriteType.h
@@ -26,11 +26,10 @@
 
 class CRewriteType : public IRewrite {
 public:
-	CRewriteType(const char* name, unsigned int fromSlot, unsigned int fromTG, unsigned int toSlot, unsigned int toId, bool trace);
+	CRewriteType(const char* name, unsigned int fromSlot, unsigned int fromTG, unsigned int toSlot, unsigned int toId);
 	virtual ~CRewriteType();
 
-	virtual bool processRF(CDMRData& data);
-	virtual bool processNet(CDMRData& data);
+	virtual bool process(CDMRData& data, bool trace);
 
 private:
 	const char*      m_name;
@@ -38,11 +37,9 @@ private:
 	unsigned int     m_fromTG;
 	unsigned int     m_toSlot;
 	unsigned int     m_toId;
-	bool             m_trace;
 	CDMRLC           m_lc;
 	CDMREmbeddedData m_embeddedLC;
 
-	bool process(CDMRData& data);
 	void processHeader(CDMRData& data, unsigned char dataType);
 	void processVoice(CDMRData& data);
 };