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https://github.com/g4klx/DMRGateway
synced 2025-12-24 07:15:38 +08:00
Handle TA and Embedded GPS data correctly.
This commit is contained in:
@@ -171,22 +171,22 @@ m_dmr2Passalls()
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CDMRGateway::~CDMRGateway()
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{
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for (std::vector<IRewrite*>::iterator it = m_dmr1NetRewrites.begin(); it != m_dmr1NetRewrites.end(); ++it)
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for (std::vector<CRewrite*>::iterator it = m_dmr1NetRewrites.begin(); it != m_dmr1NetRewrites.end(); ++it)
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delete *it;
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for (std::vector<IRewrite*>::iterator it = m_dmr1RFRewrites.begin(); it != m_dmr1RFRewrites.end(); ++it)
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for (std::vector<CRewrite*>::iterator it = m_dmr1RFRewrites.begin(); it != m_dmr1RFRewrites.end(); ++it)
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delete *it;
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for (std::vector<IRewrite*>::iterator it = m_dmr2NetRewrites.begin(); it != m_dmr2NetRewrites.end(); ++it)
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for (std::vector<CRewrite*>::iterator it = m_dmr2NetRewrites.begin(); it != m_dmr2NetRewrites.end(); ++it)
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delete *it;
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for (std::vector<IRewrite*>::iterator it = m_dmr2RFRewrites.begin(); it != m_dmr2RFRewrites.end(); ++it)
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for (std::vector<CRewrite*>::iterator it = m_dmr2RFRewrites.begin(); it != m_dmr2RFRewrites.end(); ++it)
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delete *it;
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for (std::vector<IRewrite*>::iterator it = m_dmr1Passalls.begin(); it != m_dmr1Passalls.end(); ++it)
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for (std::vector<CRewrite*>::iterator it = m_dmr1Passalls.begin(); it != m_dmr1Passalls.end(); ++it)
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delete *it;
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for (std::vector<IRewrite*>::iterator it = m_dmr2Passalls.begin(); it != m_dmr2Passalls.end(); ++it)
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for (std::vector<CRewrite*>::iterator it = m_dmr2Passalls.begin(); it != m_dmr2Passalls.end(); ++it)
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delete *it;
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delete m_rpt1Rewrite;
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@@ -610,7 +610,7 @@ int CDMRGateway::run()
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if (m_dmrNetwork1 != NULL) {
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// Rewrite the slot and/or TG or neither
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for (std::vector<IRewrite*>::iterator it = m_dmr1RFRewrites.begin(); it != m_dmr1RFRewrites.end(); ++it) {
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for (std::vector<CRewrite*>::iterator it = m_dmr1RFRewrites.begin(); it != m_dmr1RFRewrites.end(); ++it) {
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bool ret = (*it)->process(data, trace);
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if (ret) {
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rewritten = true;
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@@ -630,7 +630,7 @@ int CDMRGateway::run()
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if (!rewritten) {
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if (m_dmrNetwork2 != NULL) {
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// Rewrite the slot and/or TG or neither
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for (std::vector<IRewrite*>::iterator it = m_dmr2RFRewrites.begin(); it != m_dmr2RFRewrites.end(); ++it) {
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for (std::vector<CRewrite*>::iterator it = m_dmr2RFRewrites.begin(); it != m_dmr2RFRewrites.end(); ++it) {
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bool ret = (*it)->process(data, trace);
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if (ret) {
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rewritten = true;
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@@ -650,7 +650,7 @@ int CDMRGateway::run()
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if (!rewritten) {
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if (m_dmrNetwork1 != NULL) {
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for (std::vector<IRewrite*>::iterator it = m_dmr1Passalls.begin(); it != m_dmr1Passalls.end(); ++it) {
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for (std::vector<CRewrite*>::iterator it = m_dmr1Passalls.begin(); it != m_dmr1Passalls.end(); ++it) {
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bool ret = (*it)->process(data, trace);
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if (ret) {
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rewritten = true;
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@@ -670,7 +670,7 @@ int CDMRGateway::run()
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if (!rewritten) {
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if (m_dmrNetwork2 != NULL) {
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for (std::vector<IRewrite*>::iterator it = m_dmr2Passalls.begin(); it != m_dmr2Passalls.end(); ++it) {
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for (std::vector<CRewrite*>::iterator it = m_dmr2Passalls.begin(); it != m_dmr2Passalls.end(); ++it) {
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bool ret = (*it)->process(data, trace);
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if (ret) {
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rewritten = true;
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@@ -752,7 +752,7 @@ int CDMRGateway::run()
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// Rewrite the slot and/or TG or neither
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bool rewritten = false;
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for (std::vector<IRewrite*>::iterator it = m_dmr1NetRewrites.begin(); it != m_dmr1NetRewrites.end(); ++it) {
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for (std::vector<CRewrite*>::iterator it = m_dmr1NetRewrites.begin(); it != m_dmr1NetRewrites.end(); ++it) {
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bool ret = (*it)->process(data, trace);
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if (ret) {
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rewritten = true;
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@@ -797,7 +797,7 @@ int CDMRGateway::run()
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// Rewrite the slot and/or TG or neither
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bool rewritten = false;
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for (std::vector<IRewrite*>::iterator it = m_dmr2NetRewrites.begin(); it != m_dmr2NetRewrites.end(); ++it) {
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for (std::vector<CRewrite*>::iterator it = m_dmr2NetRewrites.begin(); it != m_dmr2NetRewrites.end(); ++it) {
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bool ret = (*it)->process(data, trace);
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if (ret) {
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rewritten = true;
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