From 8fc9872aaaaec6520f1aa5406c8a9f31942edf34 Mon Sep 17 00:00:00 2001 From: Jonathan Naylor Date: Wed, 1 Apr 2020 22:56:48 +0100 Subject: [PATCH] Finish off the translation logic. --- DMRGateway.cpp | 10 ++++---- RewriteDynTGNet.cpp | 43 ++++++++++----------------------- RewriteDynTGNet.h | 5 +--- RewriteDynTGRF.cpp | 59 ++++++++++++++++++++++++++------------------- Version.h | 4 +-- 5 files changed, 55 insertions(+), 66 deletions(-) diff --git a/DMRGateway.cpp b/DMRGateway.cpp index a7a8bd9..54f9b62 100644 --- a/DMRGateway.cpp +++ b/DMRGateway.cpp @@ -1339,7 +1339,7 @@ bool CDMRGateway::createDMRNetwork1() for (std::vector::const_iterator it = dynRewrites.begin(); it != dynRewrites.end(); ++it) { LogInfo(" Dyn Rewrite: %u:TG%u-%u:TG%u <-> %u:TG%u (disc %u:TG%u)", (*it).m_slot, (*it).m_fromTG, (*it).m_slot, (*it).m_fromTG + (*it).m_range - 1U, (*it).m_slot, (*it).m_toTG, (*it).m_slot, (*it).m_discTG); - CRewriteDynTGNet* netRewriteDynTG = new CRewriteDynTGNet(m_dmr1Name, (*it).m_slot, (*it).m_fromTG, (*it).m_toTG, (*it).m_discTG, (*it).m_range); + CRewriteDynTGNet* netRewriteDynTG = new CRewriteDynTGNet(m_dmr1Name, (*it).m_slot, (*it).m_toTG); CRewriteDynTGRF* rfRewriteDynTG = new CRewriteDynTGRF(m_dmr1Name, (*it).m_slot, (*it).m_fromTG, (*it).m_toTG, (*it).m_discTG, (*it).m_range, netRewriteDynTG); m_dmr1RFRewrites.push_back(rfRewriteDynTG); @@ -1488,7 +1488,7 @@ bool CDMRGateway::createDMRNetwork2() for (std::vector::const_iterator it = dynRewrites.begin(); it != dynRewrites.end(); ++it) { LogInfo(" Dyn Rewrite: %u:TG%u-%u:TG%u <-> %u:TG%u (disc %u:TG%u)", (*it).m_slot, (*it).m_fromTG, (*it).m_slot, (*it).m_fromTG + (*it).m_range - 1U, (*it).m_slot, (*it).m_toTG, (*it).m_slot, (*it).m_discTG); - CRewriteDynTGNet* netRewriteDynTG = new CRewriteDynTGNet(m_dmr2Name, (*it).m_slot, (*it).m_fromTG, (*it).m_toTG, (*it).m_discTG, (*it).m_range); + CRewriteDynTGNet* netRewriteDynTG = new CRewriteDynTGNet(m_dmr2Name, (*it).m_slot, (*it).m_toTG); CRewriteDynTGRF* rfRewriteDynTG = new CRewriteDynTGRF(m_dmr2Name, (*it).m_slot, (*it).m_fromTG, (*it).m_toTG, (*it).m_discTG, (*it).m_range, netRewriteDynTG); m_dmr2RFRewrites.push_back(rfRewriteDynTG); @@ -1637,7 +1637,7 @@ bool CDMRGateway::createDMRNetwork3() for (std::vector::const_iterator it = dynRewrites.begin(); it != dynRewrites.end(); ++it) { LogInfo(" Dyn Rewrite: %u:TG%u-%u:TG%u <-> %u:TG%u (disc %u:TG%u)", (*it).m_slot, (*it).m_fromTG, (*it).m_slot, (*it).m_fromTG + (*it).m_range - 1U, (*it).m_slot, (*it).m_toTG, (*it).m_slot, (*it).m_discTG); - CRewriteDynTGNet* netRewriteDynTG = new CRewriteDynTGNet(m_dmr3Name, (*it).m_slot, (*it).m_fromTG, (*it).m_toTG, (*it).m_discTG, (*it).m_range); + CRewriteDynTGNet* netRewriteDynTG = new CRewriteDynTGNet(m_dmr3Name, (*it).m_slot, (*it).m_toTG); CRewriteDynTGRF* rfRewriteDynTG = new CRewriteDynTGRF(m_dmr3Name, (*it).m_slot, (*it).m_fromTG, (*it).m_toTG, (*it).m_discTG, (*it).m_range, netRewriteDynTG); m_dmr3RFRewrites.push_back(rfRewriteDynTG); @@ -1786,7 +1786,7 @@ bool CDMRGateway::createDMRNetwork4() for (std::vector::const_iterator it = dynRewrites.begin(); it != dynRewrites.end(); ++it) { LogInfo(" Dyn Rewrite: %u:TG%u-%u:TG%u <-> %u:TG%u (disc %u:TG%u)", (*it).m_slot, (*it).m_fromTG, (*it).m_slot, (*it).m_fromTG + (*it).m_range - 1U, (*it).m_slot, (*it).m_toTG, (*it).m_slot, (*it).m_discTG); - CRewriteDynTGNet* netRewriteDynTG = new CRewriteDynTGNet(m_dmr4Name, (*it).m_slot, (*it).m_fromTG, (*it).m_toTG, (*it).m_discTG, (*it).m_range); + CRewriteDynTGNet* netRewriteDynTG = new CRewriteDynTGNet(m_dmr4Name, (*it).m_slot, (*it).m_toTG); CRewriteDynTGRF* rfRewriteDynTG = new CRewriteDynTGRF(m_dmr4Name, (*it).m_slot, (*it).m_fromTG, (*it).m_toTG, (*it).m_discTG, (*it).m_range, netRewriteDynTG); m_dmr4RFRewrites.push_back(rfRewriteDynTG); @@ -1935,7 +1935,7 @@ bool CDMRGateway::createDMRNetwork5() for (std::vector::const_iterator it = dynRewrites.begin(); it != dynRewrites.end(); ++it) { LogInfo(" Dyn Rewrite: %u:TG%u-%u:TG%u <-> %u:TG%u (disc %u:TG%u)", (*it).m_slot, (*it).m_fromTG, (*it).m_slot, (*it).m_fromTG + (*it).m_range - 1U, (*it).m_slot, (*it).m_toTG, (*it).m_slot, (*it).m_discTG); - CRewriteDynTGNet* netRewriteDynTG = new CRewriteDynTGNet(m_dmr5Name, (*it).m_slot, (*it).m_fromTG, (*it).m_toTG, (*it).m_discTG, (*it).m_range); + CRewriteDynTGNet* netRewriteDynTG = new CRewriteDynTGNet(m_dmr5Name, (*it).m_slot, (*it).m_toTG); CRewriteDynTGRF* rfRewriteDynTG = new CRewriteDynTGRF(m_dmr5Name, (*it).m_slot, (*it).m_fromTG, (*it).m_toTG, (*it).m_discTG, (*it).m_range, netRewriteDynTG); m_dmr5RFRewrites.push_back(rfRewriteDynTG); diff --git a/RewriteDynTGNet.cpp b/RewriteDynTGNet.cpp index 3e4f99c..889117e 100644 --- a/RewriteDynTGNet.cpp +++ b/RewriteDynTGNet.cpp @@ -24,14 +24,11 @@ #include #include -CRewriteDynTGNet::CRewriteDynTGNet(const std::string& name, unsigned int slot, unsigned int fromTG, unsigned int toTG, unsigned int discTG, unsigned int range) : +CRewriteDynTGNet::CRewriteDynTGNet(const std::string& name, unsigned int slot, unsigned int toTG) : CRewrite(), m_name(name), m_slot(slot), -m_fromTGStart(fromTG), -m_fromTGEnd(fromTG + range - 1U), m_toTG(toTG), -m_discTG(discTG), m_currentTG(0U) { assert(slot == 1U || slot == 2U); @@ -47,38 +44,24 @@ bool CRewriteDynTGNet::process(CDMRData& data, bool trace) unsigned int dstId = data.getDstId(); unsigned int slotNo = data.getSlotNo(); - if (flco != FLCO_GROUP || slotNo != m_fromSlot || dstId < m_fromTGStart || dstId > m_fromTGEnd) { - if (trace) { - if (m_fromTGStart == m_fromTGEnd) - LogDebug("Rule Trace,\tRewriteDynTGNet from %s Slot=%u Dst=TG%u: not matched", m_name.c_str(), m_fromSlot, m_fromTGStart); - else - LogDebug("Rule Trace,\tRewriteDynTGNet from %s Slot=%u Dst=TG%u-TG%u: not matched", m_name.c_str(), m_fromSlot, m_fromTGStart, m_fromTGEnd); - } + if (flco != FLCO_GROUP || slotNo != m_slot || dstId != m_currentTG) { + if (trace) + LogDebug("Rule Trace,\tRewriteDynTGNet from %s Slot=%u Dst=TG%u: not matched", m_name.c_str(), m_slot, m_currentTG); return false; } - if (m_fromSlot != m_toSlot) - data.setSlotNo(m_toSlot); + data.setDstId(m_toTG); - if (m_fromTGStart != m_toTGStart) { - unsigned int newTG = dstId + m_toTGStart - m_fromTGStart; - data.setDstId(newTG); + processMessage(data); - processMessage(data); - } - - if (trace) { - if (m_fromTGStart == m_fromTGEnd) - LogDebug("Rule Trace,\tRewriteDynTGNet from %s Slot=%u Dst=TG%u: matched", m_name.c_str(), m_fromSlot, m_fromTGStart); - else - LogDebug("Rule Trace,\tRewriteDynTGNet from %s Slot=%u Dst=TG%u-TG%u: matched", m_name.c_str(), m_fromSlot, m_fromTGStart, m_fromTGEnd); - - if (m_toTGStart == m_toTGEnd) - LogDebug("Rule Trace,\tRewriteDynTGNet to %s Slot=%u Dst=TG%u", m_name.c_str(), m_toSlot, m_toTGStart); - else - LogDebug("Rule Trace,\tRewriteDynTGNet to %s Slot=%u Dst=TG%u-TG%u", m_name.c_str(), m_toSlot, m_toTGStart, m_toTGEnd); - } + if (trace) + LogDebug("Rule Trace,\tRewriteDynTGNet from %s Slot=%u Dst=TG%u: matched", m_name.c_str(), m_slot, m_currentTG); return true; } + +void CRewriteDynTGNet::setCurrentTG(unsigned int currentTG) +{ + m_currentTG = currentTG; +} diff --git a/RewriteDynTGNet.h b/RewriteDynTGNet.h index feb6a83..fb04031 100644 --- a/RewriteDynTGNet.h +++ b/RewriteDynTGNet.h @@ -26,7 +26,7 @@ class CRewriteDynTGNet : public CRewrite { public: - CRewriteDynTGNet(const std::string& name, unsigned int slot, unsigned int fromTG, unsigned int toTG, unsigned int discTG, unsigned int range); + CRewriteDynTGNet(const std::string& name, unsigned int slot, unsigned int toTG); virtual ~CRewriteDynTGNet(); virtual bool process(CDMRData& data, bool trace); @@ -36,10 +36,7 @@ public: private: std::string m_name; unsigned int m_slot; - unsigned int m_fromTGStart; - unsigned int m_fromTGEnd; unsigned int m_toTG; - unsigned int m_discTG; unsigned int m_currentTG; }; diff --git a/RewriteDynTGRF.cpp b/RewriteDynTGRF.cpp index eaa9aab..a8cdb7f 100644 --- a/RewriteDynTGRF.cpp +++ b/RewriteDynTGRF.cpp @@ -49,38 +49,47 @@ bool CRewriteDynTGRF::process(CDMRData& data, bool trace) unsigned int dstId = data.getDstId(); unsigned int slotNo = data.getSlotNo(); - if (flco != FLCO_GROUP || slotNo != m_fromSlot || dstId < m_fromTGStart || dstId > m_fromTGEnd) { - if (trace) { - if (m_fromTGStart == m_fromTGEnd) - LogDebug("Rule Trace,\tRewriteDynTGRF from %s Slot=%u Dst=TG%u: not matched", m_name.c_str(), m_fromSlot, m_fromTGStart); - else - LogDebug("Rule Trace,\tRewriteDynTGRF from %s Slot=%u Dst=TG%u-TG%u: not matched", m_name.c_str(), m_fromSlot, m_fromTGStart, m_fromTGEnd); - } - - return false; - } - - if (m_fromSlot != m_toSlot) - data.setSlotNo(m_toSlot); - - if (m_fromTGStart != m_toTGStart) { - unsigned int newTG = dstId + m_toTGStart - m_fromTGStart; - data.setDstId(newTG); + if (flco == FLCO_GROUP && slotNo == m_slot && dstId == m_toTG && m_currentTG != 0U) { + data.setDstId(m_currentTG); processMessage(data); + + if (trace) + LogDebug("Rule Trace,\tRewriteDynTGRF from %s Slot=%u Dst=TG%u: matched", m_name.c_str(), m_slot, m_toTG); + + return true; + } + + if (flco == FLCO_GROUP && slotNo == m_slot && dstId == m_discTG && m_currentTG != 0U) { + if (trace) + LogDebug("Rule Trace,\tRewriteDynTGRF from %s Slot=%u Dst=TG%u: matched", m_name.c_str(), m_slot, m_discTG); + + m_rewriteNet->setCurrentTG(0U); + m_currentTG = 0U; + + return true; + } + + if (flco == FLCO_GROUP && slotNo == m_slot && dstId >= m_fromTGStart && dstId <= m_fromTGEnd) { + if (trace) { + if (m_fromTGStart == m_fromTGEnd) + LogDebug("Rule Trace,\tRewriteDynTGRF from %s Slot=%u Dst=TG%u: matched", m_name.c_str(), m_slot, m_fromTGStart); + else + LogDebug("Rule Trace,\tRewriteDynTGRF from %s Slot=%u Dst=TG%u-TG%u: matched", m_name.c_str(), m_slot, m_fromTGStart, m_fromTGEnd); + } + + m_rewriteNet->setCurrentTG(dstId); + m_currentTG = dstId; + + return true; } if (trace) { if (m_fromTGStart == m_fromTGEnd) - LogDebug("Rule Trace,\tRewriteDynTGRF from %s Slot=%u Dst=TG%u: matched", m_name.c_str(), m_fromSlot, m_fromTGStart); + LogDebug("Rule Trace,\tRewriteDynTGRF from %s Slot=%u Dst=TG%u or Dst=TG%u or Dst=TG%u: not matched", m_name.c_str(), m_slot, m_fromTGStart, m_toTG, m_discTG); else - LogDebug("Rule Trace,\tRewriteDynTGRF from %s Slot=%u Dst=TG%u-TG%u: matched", m_name.c_str(), m_fromSlot, m_fromTGStart, m_fromTGEnd); - - if (m_toTGStart == m_toTGEnd) - LogDebug("Rule Trace,\tRewriteDynTGRF to %s Slot=%u Dst=TG%u", m_name.c_str(), m_toSlot, m_toTGStart); - else - LogDebug("Rule Trace,\tRewriteDynTGRF to %s Slot=%u Dst=TG%u-TG%u", m_name.c_str(), m_toSlot, m_toTGStart, m_toTGEnd); + LogDebug("Rule Trace,\tRewriteDynTGRF from %s Slot=%u Dst=TG%u-TG%u or Dst=TG%u or Dst=TG%u: not matched", m_name.c_str(), m_slot, m_fromTGStart, m_fromTGEnd, m_toTG, m_discTG); } - return true; + return false; } diff --git a/Version.h b/Version.h index bd50711..726b272 100644 --- a/Version.h +++ b/Version.h @@ -1,5 +1,5 @@ /* - * Copyright (C) 2015-2019 by Jonathan Naylor G4KLX + * Copyright (C) 2015-2020 by Jonathan Naylor G4KLX * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -19,6 +19,6 @@ #if !defined(VERSION_H) #define VERSION_H -const char* VERSION = "20190717"; +const char* VERSION = "20200401"; #endif