From 92bda23094580b171c681fc1063de15236011040 Mon Sep 17 00:00:00 2001 From: Jonathan Naylor Date: Sat, 27 May 2017 16:26:52 +0100 Subject: [PATCH] Split RF and network processing functionality. --- DMRGateway.cpp | 16 ++++++++-------- Rewrite.h | 3 ++- RewritePC.cpp | 10 ++++++++++ RewritePC.h | 4 +++- RewriteSrc.cpp | 10 ++++++++++ RewriteSrc.h | 4 +++- RewriteTG.cpp | 10 ++++++++++ RewriteTG.h | 4 +++- RewriteType.cpp | 10 ++++++++++ RewriteType.h | 4 +++- 10 files changed, 62 insertions(+), 13 deletions(-) diff --git a/DMRGateway.cpp b/DMRGateway.cpp index aeb4ab0..9cfc328 100644 --- a/DMRGateway.cpp +++ b/DMRGateway.cpp @@ -346,12 +346,12 @@ int CDMRGateway::run() FLCO flco = data.getFLCO(); if (flco == FLCO_GROUP && slotNo == m_xlx1Slot && dstId == m_xlx1TG) { - m_xlx1Rewrite->process(data); + m_xlx1Rewrite->processRF(data); m_xlxNetwork1->write(data); status[slotNo] = DMRGWS_XLXREFLECTOR1; timer[slotNo]->start(); } else if (flco == FLCO_GROUP && slotNo == m_xlx2Slot && dstId == m_xlx2TG) { - m_xlx2Rewrite->process(data); + m_xlx2Rewrite->processRF(data); m_xlxNetwork2->write(data); status[slotNo] = DMRGWS_XLXREFLECTOR2; timer[slotNo]->start(); @@ -423,7 +423,7 @@ int CDMRGateway::run() if (m_dmrNetwork1 != NULL) { // Rewrite the slot and/or TG or neither for (std::vector::iterator it = m_dmr1RFRewrites.begin(); it != m_dmr1RFRewrites.end(); ++it) { - bool ret = (*it)->process(data); + bool ret = (*it)->processRF(data); if (ret) { rewritten = true; break; @@ -444,7 +444,7 @@ int CDMRGateway::run() if (m_dmrNetwork2 != NULL) { // Rewrite the slot and/or TG or neither for (std::vector::iterator it = m_dmr2RFRewrites.begin(); it != m_dmr2RFRewrites.end(); ++it) { - bool ret = (*it)->process(data); + bool ret = (*it)->processRF(data); if (ret) { rewritten = true; break; @@ -468,7 +468,7 @@ int CDMRGateway::run() ret = m_xlxNetwork1->read(data); if (ret) { if (status[m_xlx1Slot] == DMRGWS_NONE || status[m_xlx1Slot] == DMRGWS_XLXREFLECTOR1) { - bool ret = m_rpt1Rewrite->process(data); + bool ret = m_rpt1Rewrite->processNet(data); if (ret) { m_repeater->write(data); status[m_xlx1Slot] = DMRGWS_XLXREFLECTOR1; @@ -487,7 +487,7 @@ int CDMRGateway::run() ret = m_xlxNetwork2->read(data); if (ret) { if (status[m_xlx2Slot] == DMRGWS_NONE || status[m_xlx2Slot] == DMRGWS_XLXREFLECTOR2) { - bool ret = m_rpt2Rewrite->process(data); + bool ret = m_rpt2Rewrite->processNet(data); if (ret) { m_repeater->write(data); status[m_xlx2Slot] = DMRGWS_XLXREFLECTOR2; @@ -509,7 +509,7 @@ int CDMRGateway::run() // Rewrite the slot and/or TG or neither bool rewritten = false; for (std::vector::iterator it = m_dmr1NetRewrites.begin(); it != m_dmr1NetRewrites.end(); ++it) { - bool ret = (*it)->process(data); + bool ret = (*it)->processNet(data); if (ret) { rewritten = true; break; @@ -536,7 +536,7 @@ int CDMRGateway::run() // Rewrite the slot and/or TG or neither bool rewritten = false; for (std::vector::iterator it = m_dmr2NetRewrites.begin(); it != m_dmr2NetRewrites.end(); ++it) { - bool ret = (*it)->process(data); + bool ret = (*it)->processNet(data); if (ret) { rewritten = true; break; diff --git a/Rewrite.h b/Rewrite.h index 5556657..c33723c 100644 --- a/Rewrite.h +++ b/Rewrite.h @@ -25,7 +25,8 @@ class IRewrite { public: virtual ~IRewrite() = 0; - virtual bool process(CDMRData& data) = 0; + virtual bool processRF(CDMRData& data) = 0; + virtual bool processNet(CDMRData& data) = 0; private: }; diff --git a/RewritePC.cpp b/RewritePC.cpp index 8cf295c..e3b281e 100644 --- a/RewritePC.cpp +++ b/RewritePC.cpp @@ -42,6 +42,16 @@ CRewritePC::~CRewritePC() { } +bool CRewritePC::processRF(CDMRData& data) +{ + return process(data); +} + +bool CRewritePC::processNet(CDMRData& data) +{ + return process(data); +} + bool CRewritePC::process(CDMRData& data) { FLCO flco = data.getFLCO(); diff --git a/RewritePC.h b/RewritePC.h index 1299b71..550ad71 100644 --- a/RewritePC.h +++ b/RewritePC.h @@ -29,7 +29,8 @@ public: CRewritePC(const char* name, unsigned int fromSlot, unsigned int fromId, unsigned int toSlot, unsigned int toId, unsigned int range); virtual ~CRewritePC(); - virtual bool process(CDMRData& data); + virtual bool processRF(CDMRData& data); + virtual bool processNet(CDMRData& data); private: const char* m_name; @@ -41,6 +42,7 @@ private: CDMRLC m_lc; CDMREmbeddedData m_embeddedLC; + bool process(CDMRData& data); void processHeader(CDMRData& data, unsigned int dstId, unsigned char dataType); void processVoice(CDMRData& data, unsigned int dstId); }; diff --git a/RewriteSrc.cpp b/RewriteSrc.cpp index 55838ce..8aa9a62 100644 --- a/RewriteSrc.cpp +++ b/RewriteSrc.cpp @@ -45,6 +45,16 @@ CRewriteSrc::~CRewriteSrc() { } +bool CRewriteSrc::processRF(CDMRData& data) +{ + return process(data); +} + +bool CRewriteSrc::processNet(CDMRData& data) +{ + return process(data); +} + bool CRewriteSrc::process(CDMRData& data) { FLCO flco = data.getFLCO(); diff --git a/RewriteSrc.h b/RewriteSrc.h index 2b1bf41..d68ef79 100644 --- a/RewriteSrc.h +++ b/RewriteSrc.h @@ -29,7 +29,8 @@ public: CRewriteSrc(const char* name, unsigned int fromSlot, unsigned int fromId, unsigned int toSlot, unsigned int toTG, unsigned int range); virtual ~CRewriteSrc(); - virtual bool process(CDMRData& data); + virtual bool processRF(CDMRData& data); + virtual bool processNet(CDMRData& data); private: const char* m_name; @@ -41,6 +42,7 @@ private: CDMRLC m_lc; CDMREmbeddedData m_embeddedLC; + bool process(CDMRData& data); void processHeader(CDMRData& data, unsigned char dataType); void processVoice(CDMRData& data); }; diff --git a/RewriteTG.cpp b/RewriteTG.cpp index 0bbca05..8f44e4a 100644 --- a/RewriteTG.cpp +++ b/RewriteTG.cpp @@ -42,6 +42,16 @@ CRewriteTG::~CRewriteTG() { } +bool CRewriteTG::processRF(CDMRData& data) +{ + return process(data); +} + +bool CRewriteTG::processNet(CDMRData& data) +{ + return process(data); +} + bool CRewriteTG::process(CDMRData& data) { FLCO flco = data.getFLCO(); diff --git a/RewriteTG.h b/RewriteTG.h index 6565df3..5f2a7f8 100644 --- a/RewriteTG.h +++ b/RewriteTG.h @@ -29,7 +29,8 @@ public: CRewriteTG(const char*name, unsigned int fromSlot, unsigned int fromTG, unsigned int toSlot, unsigned int toTG, unsigned int range); virtual ~CRewriteTG(); - virtual bool process(CDMRData& data); + virtual bool processRF(CDMRData& data); + virtual bool processNet(CDMRData& data); private: const char* m_name; @@ -41,6 +42,7 @@ private: CDMRLC m_lc; CDMREmbeddedData m_embeddedLC; + bool process(CDMRData& data); void processHeader(CDMRData& data, unsigned int tg, unsigned char dataType); void processVoice(CDMRData& data, unsigned int tg); }; diff --git a/RewriteType.cpp b/RewriteType.cpp index e7251a4..a3936da 100644 --- a/RewriteType.cpp +++ b/RewriteType.cpp @@ -42,6 +42,16 @@ CRewriteType::~CRewriteType() { } +bool CRewriteType::processRF(CDMRData& data) +{ + return process(data); +} + +bool CRewriteType::processNet(CDMRData& data) +{ + return process(data); +} + bool CRewriteType::process(CDMRData& data) { FLCO flco = data.getFLCO(); diff --git a/RewriteType.h b/RewriteType.h index ac47b87..c8de2f2 100644 --- a/RewriteType.h +++ b/RewriteType.h @@ -29,7 +29,8 @@ public: CRewriteType(const char* name, unsigned int fromSlot, unsigned int fromTG, unsigned int toSlot, unsigned int toId); virtual ~CRewriteType(); - virtual bool process(CDMRData& data); + virtual bool processRF(CDMRData& data); + virtual bool processNet(CDMRData& data); private: const char* m_name; @@ -40,6 +41,7 @@ private: CDMRLC m_lc; CDMREmbeddedData m_embeddedLC; + bool process(CDMRData& data); void processHeader(CDMRData& data, unsigned char dataType); void processVoice(CDMRData& data); };