mirror of
https://github.com/g4klx/DMRGateway
synced 2025-12-22 22:45:36 +08:00
Modify Type Rewrite to handle BM Echo.
This commit is contained in:
8
Conf.cpp
8
Conf.cpp
@@ -242,9 +242,9 @@ bool CConf::read()
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if (p1 != NULL && p2 != NULL && p3 != NULL && p4 != NULL) {
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if (p1 != NULL && p2 != NULL && p3 != NULL && p4 != NULL) {
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CTypeRewriteStruct rewrite;
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CTypeRewriteStruct rewrite;
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rewrite.m_fromSlot = ::atoi(p1);
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rewrite.m_fromSlot = ::atoi(p1);
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rewrite.m_fromId = ::atoi(p2);
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rewrite.m_fromTG = ::atoi(p2);
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rewrite.m_toSlot = ::atoi(p3);
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rewrite.m_toSlot = ::atoi(p3);
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rewrite.m_toTG = ::atoi(p4);
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rewrite.m_toId = ::atoi(p4);
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m_dmrNetwork1TypeRewrites.push_back(rewrite);
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m_dmrNetwork1TypeRewrites.push_back(rewrite);
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}
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}
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} else if (::strcmp(key, "SrcRewrite") == 0) {
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} else if (::strcmp(key, "SrcRewrite") == 0) {
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@@ -318,9 +318,9 @@ bool CConf::read()
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if (p1 != NULL && p2 != NULL && p3 != NULL && p4 != NULL) {
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if (p1 != NULL && p2 != NULL && p3 != NULL && p4 != NULL) {
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CTypeRewriteStruct rewrite;
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CTypeRewriteStruct rewrite;
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rewrite.m_fromSlot = ::atoi(p1);
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rewrite.m_fromSlot = ::atoi(p1);
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rewrite.m_fromId = ::atoi(p2);
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rewrite.m_fromTG = ::atoi(p2);
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rewrite.m_toSlot = ::atoi(p3);
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rewrite.m_toSlot = ::atoi(p3);
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rewrite.m_toTG = ::atoi(p4);
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rewrite.m_toId = ::atoi(p4);
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m_dmrNetwork2TypeRewrites.push_back(rewrite);
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m_dmrNetwork2TypeRewrites.push_back(rewrite);
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}
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}
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} else if (::strcmp(key, "SrcRewrite") == 0) {
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} else if (::strcmp(key, "SrcRewrite") == 0) {
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4
Conf.h
4
Conf.h
@@ -40,9 +40,9 @@ struct CPCRewriteStruct {
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struct CTypeRewriteStruct {
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struct CTypeRewriteStruct {
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unsigned int m_fromSlot;
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unsigned int m_fromSlot;
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unsigned int m_fromId;
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unsigned int m_fromTG;
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unsigned int m_toSlot;
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unsigned int m_toSlot;
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unsigned int m_toTG;
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unsigned int m_toId;
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};
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};
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struct CSrcRewriteStruct {
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struct CSrcRewriteStruct {
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@@ -659,11 +659,11 @@ bool CDMRGateway::createDMRNetwork1()
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std::vector<CTypeRewriteStruct> typeRewrites = m_conf.getDMRNetwork1TypeRewrites();
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std::vector<CTypeRewriteStruct> typeRewrites = m_conf.getDMRNetwork1TypeRewrites();
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for (std::vector<CTypeRewriteStruct>::const_iterator it = typeRewrites.begin(); it != typeRewrites.end(); ++it) {
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for (std::vector<CTypeRewriteStruct>::const_iterator it = typeRewrites.begin(); it != typeRewrites.end(); ++it) {
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LogInfo(" Rewrite Net: %u:%u -> %u:TG%u", (*it).m_fromSlot, (*it).m_fromId, (*it).m_toSlot, (*it).m_toTG);
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LogInfo(" Rewrite RF: %u:TG%u -> %u:%u", (*it).m_fromSlot, (*it).m_fromTG, (*it).m_toSlot, (*it).m_toId);
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CRewriteType* rewrite = new CRewriteType("DMR-1", (*it).m_fromSlot, (*it).m_fromId, (*it).m_toSlot, (*it).m_toTG);
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CRewriteType* rewrite = new CRewriteType("DMR-1", (*it).m_fromSlot, (*it).m_fromTG, (*it).m_toSlot, (*it).m_toId);
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m_dmr1NetRewrites.push_back(rewrite);
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m_dmr1RFRewrites.push_back(rewrite);
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}
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}
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std::vector<CSrcRewriteStruct> srcRewrites = m_conf.getDMRNetwork1SrcRewrites();
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std::vector<CSrcRewriteStruct> srcRewrites = m_conf.getDMRNetwork1SrcRewrites();
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@@ -748,11 +748,11 @@ bool CDMRGateway::createDMRNetwork2()
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std::vector<CTypeRewriteStruct> typeRewrites = m_conf.getDMRNetwork2TypeRewrites();
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std::vector<CTypeRewriteStruct> typeRewrites = m_conf.getDMRNetwork2TypeRewrites();
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for (std::vector<CTypeRewriteStruct>::const_iterator it = typeRewrites.begin(); it != typeRewrites.end(); ++it) {
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for (std::vector<CTypeRewriteStruct>::const_iterator it = typeRewrites.begin(); it != typeRewrites.end(); ++it) {
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LogInfo(" Rewrite Net: %u:%u -> %u:TG%u", (*it).m_fromSlot, (*it).m_fromId, (*it).m_toSlot, (*it).m_toTG);
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LogInfo(" Rewrite RF: %u:TG%u -> %u:%u", (*it).m_fromSlot, (*it).m_fromTG, (*it).m_toSlot, (*it).m_toId);
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CRewriteType* rewrite = new CRewriteType("DMR-2", (*it).m_fromSlot, (*it).m_fromId, (*it).m_toSlot, (*it).m_toTG);
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CRewriteType* rewrite = new CRewriteType("DMR-2", (*it).m_fromSlot, (*it).m_fromTG, (*it).m_toSlot, (*it).m_toId);
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m_dmr2NetRewrites.push_back(rewrite);
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m_dmr2RFRewrites.push_back(rewrite);
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}
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}
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std::vector<CSrcRewriteStruct> srcRewrites = m_conf.getDMRNetwork2SrcRewrites();
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std::vector<CSrcRewriteStruct> srcRewrites = m_conf.getDMRNetwork2SrcRewrites();
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@@ -42,8 +42,9 @@ TGRewrite=1,9,1,9,1
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TGRewrite=2,9,2,9,1
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TGRewrite=2,9,2,9,1
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# Reflector control command slot 2 94000->4000 to 95000->5000
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# Reflector control command slot 2 94000->4000 to 95000->5000
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PCRewrite=2,94000,2,4000,1001
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PCRewrite=2,94000,2,4000,1001
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# Echo on slot 1 9990
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# Echo on RF slot 1 TG9990 to network slot 1 9990
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PCRewrite=1,9990,2,9990,1
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TypeRewrite=1,9990,1,9990
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SrcRewrite=1,9990,1,9990,1
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# Reflector status returns
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# Reflector status returns
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SrcRewrite=2,4000,2,9,1001
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SrcRewrite=2,4000,2,9,1001
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Password=PASSWORD
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Password=PASSWORD
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@@ -25,13 +25,13 @@
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#include <cstdio>
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#include <cstdio>
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#include <cassert>
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#include <cassert>
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CRewriteType::CRewriteType(const char* name, unsigned int fromSlot, unsigned int fromId, unsigned int toSlot, unsigned int toTG) :
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CRewriteType::CRewriteType(const char* name, unsigned int fromSlot, unsigned int fromTG, unsigned int toSlot, unsigned int toId) :
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m_name(name),
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m_name(name),
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m_fromSlot(fromSlot),
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m_fromSlot(fromSlot),
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m_fromId(fromId),
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m_fromTG(fromTG),
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m_toSlot(toSlot),
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m_toSlot(toSlot),
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m_toTG(toTG),
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m_toId(toId),
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m_lc(FLCO_GROUP, 0U, toTG),
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m_lc(FLCO_USER_USER, 0U, toId),
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m_embeddedLC()
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m_embeddedLC()
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{
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{
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assert(fromSlot == 1U || fromSlot == 2U);
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assert(fromSlot == 1U || fromSlot == 2U);
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@@ -48,14 +48,14 @@ bool CRewriteType::process(CDMRData& data)
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unsigned int dstId = data.getDstId();
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unsigned int dstId = data.getDstId();
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unsigned int slotNo = data.getSlotNo();
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unsigned int slotNo = data.getSlotNo();
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if (flco != FLCO_USER_USER || slotNo != m_fromSlot || dstId != m_fromId)
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if (flco != FLCO_GROUP || slotNo != m_fromSlot || dstId != m_fromTG)
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return false;
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return false;
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if (m_fromSlot != m_toSlot)
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if (m_fromSlot != m_toSlot)
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data.setSlotNo(m_toSlot);
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data.setSlotNo(m_toSlot);
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data.setDstId(m_toTG);
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data.setDstId(m_toId);
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data.setFLCO(FLCO_GROUP);
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data.setFLCO(FLCO_USER_USER);
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unsigned char dataType = data.getDataType();
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unsigned char dataType = data.getDataType();
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@@ -86,8 +86,6 @@ void CRewriteType::processHeader(CDMRData& data, unsigned char dataType)
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m_embeddedLC.setLC(m_lc);
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m_embeddedLC.setLC(m_lc);
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}
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}
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LogDebug("%s, Private call to TG rewrite of id: %u", m_name, m_fromId);
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unsigned char buffer[DMR_FRAME_LENGTH_BYTES];
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unsigned char buffer[DMR_FRAME_LENGTH_BYTES];
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data.getData(buffer);
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data.getData(buffer);
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@@ -26,7 +26,7 @@
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class CRewriteType : public IRewrite {
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class CRewriteType : public IRewrite {
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public:
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public:
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CRewriteType(const char* name, unsigned int fromSlot, unsigned int fromId, unsigned int toSlot, unsigned int toTG);
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CRewriteType(const char* name, unsigned int fromSlot, unsigned int fromTG, unsigned int toSlot, unsigned int toId);
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virtual ~CRewriteType();
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virtual ~CRewriteType();
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virtual bool process(CDMRData& data);
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virtual bool process(CDMRData& data);
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@@ -34,9 +34,9 @@ public:
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private:
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private:
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const char* m_name;
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const char* m_name;
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unsigned int m_fromSlot;
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unsigned int m_fromSlot;
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unsigned int m_fromId;
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unsigned int m_fromTG;
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unsigned int m_toSlot;
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unsigned int m_toSlot;
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unsigned int m_toTG;
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unsigned int m_toId;
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CDMRLC m_lc;
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CDMRLC m_lc;
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CDMREmbeddedData m_embeddedLC;
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CDMREmbeddedData m_embeddedLC;
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