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Fix the order of processing the dynamic rewrite rules.

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This commit is contained in:
Jonathan Naylor
2020-04-08 17:28:43 +01:00
parent 6b470c92a7
commit dafac8c025
4 changed files with 53 additions and 45 deletions
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84
RewriteDynTGRF.cpp
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@@ -54,43 +54,65 @@ PROCESS_RESULT CRewriteDynTGRF::process(CDMRData& data, bool trace)
unsigned int slotNo = data.getSlotNo();
unsigned char type = data.getDataType();
if (flco == FLCO_GROUP && slotNo == m_slot && dstId == m_toTG && m_currentTG != 0U) {
data.setDstId(m_currentTG);
processMessage(data);
if (flco == FLCO_GROUP && slotNo == m_slot && dstId == m_toTG) {
if (trace)
LogDebug("Rule Trace,\tRewriteDynTGRF from %s Slot=%u Dst=TG%u: matched", m_name.c_str(), m_slot, m_toTG);
return RESULT_MATCHED;
if (m_currentTG != 0U) {
data.setDstId(m_currentTG);
processMessage(data);
return RESULT_MATCHED;
} else {
return RESULT_IGNORED;
}
}
if (flco == FLCO_GROUP && std::find(m_exclTGs.cbegin(), m_exclTGs.cend(), dstId) != m_exclTGs.cend()) {
if (trace)
LogDebug("Rule Trace,\tRewriteDynTGRF from %s Slot=%u Dst=TG%u: not matched", m_name.c_str(), m_slot, dstId);
return RESULT_UNMATCHED;
}
if (flco == FLCO_USER_USER && slotNo == m_slot && dstId == m_discPC && m_currentTG != 0U) {
if (slotNo == m_slot && dstId == m_discPC) {
if (trace)
LogDebug("Rule Trace,\tRewriteDynTGRF from %s Slot=%u Dst=%u: matched", m_name.c_str(), m_slot, m_discPC);
data.setFLCO(FLCO_GROUP);
if (m_currentTG != 0U) {
data.setFLCO(FLCO_GROUP);
processMessage(data);
processMessage(data);
if (type == DT_TERMINATOR_WITH_LC) {
m_rewriteNet->setCurrentTG(0U);
m_currentTG = 0U;
if (m_voice != NULL)
m_voice->unlinked();
if (type == DT_TERMINATOR_WITH_LC) {
m_rewriteNet->setCurrentTG(0U);
m_currentTG = 0U;
if (m_voice != NULL)
m_voice->unlinked();
}
return RESULT_MATCHED;
} else {
return RESULT_IGNORED;
}
return RESULT_MATCHED;
}
if (flco == FLCO_USER_USER && slotNo == m_slot && dstId >= m_fromTGStart && dstId <= m_fromTGEnd) {
if (slotNo == m_slot && dstId == m_statusPC) {
if (trace)
LogDebug("Rule Trace,\tRewriteDynTGRF from %s Slot=%u Dst=%u: matched", m_name.c_str(), m_slot, m_statusPC);
if (type == DT_TERMINATOR_WITH_LC && m_voice != NULL) {
if (m_currentTG == 0U)
m_voice->unlinked();
else
m_voice->linkedTo(m_currentTG);
}
return RESULT_IGNORED;
}
if (std::find(m_exclTGs.cbegin(), m_exclTGs.cend(), dstId) != m_exclTGs.cend()) {
if (trace)
LogDebug("Rule Trace,\tRewriteDynTGRF from %s Slot=%u Dst=%u: matched", m_name.c_str(), m_slot, dstId);
return RESULT_IGNORED;
}
if (slotNo == m_slot && dstId >= m_fromTGStart && dstId <= m_fromTGEnd) {
if (trace) {
if (m_fromTGStart == m_fromTGEnd)
LogDebug("Rule Trace,\tRewriteDynTGRF from %s Slot=%u Dst=%u: matched", m_name.c_str(), m_slot, m_fromTGStart);
@@ -112,20 +134,6 @@ PROCESS_RESULT CRewriteDynTGRF::process(CDMRData& data, bool trace)
return RESULT_MATCHED;
}
if (flco == FLCO_USER_USER && slotNo == m_slot && dstId == m_statusPC) {
if (trace)
LogDebug("Rule Trace,\tRewriteDynTGRF from %s Slot=%u Dst=%u: matched", m_name.c_str(), m_slot, m_statusPC);
if (type == DT_TERMINATOR_WITH_LC && m_voice != NULL) {
if (m_currentTG == 0U)
m_voice->unlinked();
else
m_voice->linkedTo(m_currentTG);
}
return RESULT_IGNORED;
}
if (trace) {
if (m_fromTGStart == m_fromTGEnd)
LogDebug("Rule Trace,\tRewriteDynTGRF from %s Slot=%u Dst=%u or Dst=TG%u or Dst=%u or Dst=%u: not matched", m_name.c_str(), m_slot, m_fromTGStart, m_toTG, m_discPC, m_statusPC);