mirror of
https://github.com/g4klx/DMRGateway
synced 2025-12-23 23:05:38 +08:00
Fix the order of processing the dynamic rewrite rules.
This commit is contained in:
@@ -1352,7 +1352,7 @@ bool CDMRGateway::createDMRNetwork1()
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std::vector<CTGDynRewriteStruct> dynRewrites = m_conf.getDMRNetwork1TGDynRewrites();
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for (std::vector<CTGDynRewriteStruct>::const_iterator it = dynRewrites.begin(); it != dynRewrites.end(); ++it) {
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LogInfo(" Dyn Rewrite: %u:TG%u-%u:TG%u <-> %u:TG%u (disc %u:%u) (status %u:%u)", (*it).m_slot, (*it).m_fromTG, (*it).m_slot, (*it).m_fromTG + (*it).m_range - 1U, (*it).m_slot, (*it).m_toTG, (*it).m_slot, (*it).m_discPC, (*it).m_slot, (*it).m_statusPC);
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LogInfo(" Dyn Rewrite: %u:TG%u-%u:TG%u <-> %u:TG%u (disc %u:%u) (status %u:%u) (%u exclusions)", (*it).m_slot, (*it).m_fromTG, (*it).m_slot, (*it).m_fromTG + (*it).m_range - 1U, (*it).m_slot, (*it).m_toTG, (*it).m_slot, (*it).m_discPC, (*it).m_slot, (*it).m_statusPC, (*it).m_exclTGs.size());
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CDynVoice* voice = NULL;
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if (m_conf.getVoiceEnabled()) {
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@@ -1516,7 +1516,7 @@ bool CDMRGateway::createDMRNetwork2()
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std::vector<CTGDynRewriteStruct> dynRewrites = m_conf.getDMRNetwork2TGDynRewrites();
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for (std::vector<CTGDynRewriteStruct>::const_iterator it = dynRewrites.begin(); it != dynRewrites.end(); ++it) {
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LogInfo(" Dyn Rewrite: %u:TG%u-%u:TG%u <-> %u:TG%u (disc %u:%u) (status %u:%u)", (*it).m_slot, (*it).m_fromTG, (*it).m_slot, (*it).m_fromTG + (*it).m_range - 1U, (*it).m_slot, (*it).m_toTG, (*it).m_slot, (*it).m_discPC, (*it).m_slot, (*it).m_statusPC);
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LogInfo(" Dyn Rewrite: %u:TG%u-%u:TG%u <-> %u:TG%u (disc %u:%u) (status %u:%u) (%u exclusions)", (*it).m_slot, (*it).m_fromTG, (*it).m_slot, (*it).m_fromTG + (*it).m_range - 1U, (*it).m_slot, (*it).m_toTG, (*it).m_slot, (*it).m_discPC, (*it).m_slot, (*it).m_statusPC, (*it).m_exclTGs.size());
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CDynVoice* voice = NULL;
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if (m_conf.getVoiceEnabled()) {
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@@ -1680,7 +1680,7 @@ bool CDMRGateway::createDMRNetwork3()
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std::vector<CTGDynRewriteStruct> dynRewrites = m_conf.getDMRNetwork3TGDynRewrites();
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for (std::vector<CTGDynRewriteStruct>::const_iterator it = dynRewrites.begin(); it != dynRewrites.end(); ++it) {
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LogInfo(" Dyn Rewrite: %u:TG%u-%u:TG%u <-> %u:TG%u (disc %u:%u) (status %u:%u)", (*it).m_slot, (*it).m_fromTG, (*it).m_slot, (*it).m_fromTG + (*it).m_range - 1U, (*it).m_slot, (*it).m_toTG, (*it).m_slot, (*it).m_discPC, (*it).m_slot, (*it).m_statusPC);
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LogInfo(" Dyn Rewrite: %u:TG%u-%u:TG%u <-> %u:TG%u (disc %u:%u) (status %u:%u) (%u exclusions)", (*it).m_slot, (*it).m_fromTG, (*it).m_slot, (*it).m_fromTG + (*it).m_range - 1U, (*it).m_slot, (*it).m_toTG, (*it).m_slot, (*it).m_discPC, (*it).m_slot, (*it).m_statusPC, (*it).m_exclTGs.size());
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CDynVoice* voice = NULL;
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if (m_conf.getVoiceEnabled()) {
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@@ -1844,7 +1844,7 @@ bool CDMRGateway::createDMRNetwork4()
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std::vector<CTGDynRewriteStruct> dynRewrites = m_conf.getDMRNetwork4TGDynRewrites();
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for (std::vector<CTGDynRewriteStruct>::const_iterator it = dynRewrites.begin(); it != dynRewrites.end(); ++it) {
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LogInfo(" Dyn Rewrite: %u:TG%u-%u:TG%u <-> %u:TG%u (disc %u:%u) (status %u:%u)", (*it).m_slot, (*it).m_fromTG, (*it).m_slot, (*it).m_fromTG + (*it).m_range - 1U, (*it).m_slot, (*it).m_toTG, (*it).m_slot, (*it).m_discPC, (*it).m_slot, (*it).m_statusPC);
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LogInfo(" Dyn Rewrite: %u:TG%u-%u:TG%u <-> %u:TG%u (disc %u:%u) (status %u:%u) (%u exclusions)", (*it).m_slot, (*it).m_fromTG, (*it).m_slot, (*it).m_fromTG + (*it).m_range - 1U, (*it).m_slot, (*it).m_toTG, (*it).m_slot, (*it).m_discPC, (*it).m_slot, (*it).m_statusPC, (*it).m_exclTGs.size());
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CDynVoice* voice = NULL;
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if (m_conf.getVoiceEnabled()) {
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@@ -2008,7 +2008,7 @@ bool CDMRGateway::createDMRNetwork5()
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std::vector<CTGDynRewriteStruct> dynRewrites = m_conf.getDMRNetwork5TGDynRewrites();
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for (std::vector<CTGDynRewriteStruct>::const_iterator it = dynRewrites.begin(); it != dynRewrites.end(); ++it) {
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LogInfo(" Dyn Rewrite: %u:TG%u-%u:TG%u <-> %u:TG%u (disc %u:%u) (status %u:%u)", (*it).m_slot, (*it).m_fromTG, (*it).m_slot, (*it).m_fromTG + (*it).m_range - 1U, (*it).m_slot, (*it).m_toTG, (*it).m_slot, (*it).m_discPC, (*it).m_slot, (*it).m_statusPC);
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LogInfo(" Dyn Rewrite: %u:TG%u-%u:TG%u <-> %u:TG%u (disc %u:%u) (status %u:%u) (%u exclusions)", (*it).m_slot, (*it).m_fromTG, (*it).m_slot, (*it).m_fromTG + (*it).m_range - 1U, (*it).m_slot, (*it).m_toTG, (*it).m_slot, (*it).m_discPC, (*it).m_slot, (*it).m_statusPC, (*it).m_exclTGs.size());
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CDynVoice* voice = NULL;
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if (m_conf.getVoiceEnabled()) {
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@@ -71,7 +71,7 @@ SrcRewrite=1,9990,1,9990,1
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# Reflector status returns
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SrcRewrite=2,4000,2,9,1001
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# Dynamic rewriting of slot 2 TGs 90-999999 to TG9 to emulate reflector behaviour
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TGDynRewrite=2,90,4000,5000,9,999909,4000,5000,9900
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TGDynRewrite=2,90,4000,5000,9,999910,9900
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# Pass all of the other private traffic on slot 1 and slot 2
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PassAllPC=1
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PassAllPC=2
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@@ -54,43 +54,65 @@ PROCESS_RESULT CRewriteDynTGRF::process(CDMRData& data, bool trace)
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unsigned int slotNo = data.getSlotNo();
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unsigned char type = data.getDataType();
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if (flco == FLCO_GROUP && slotNo == m_slot && dstId == m_toTG && m_currentTG != 0U) {
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data.setDstId(m_currentTG);
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processMessage(data);
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if (flco == FLCO_GROUP && slotNo == m_slot && dstId == m_toTG) {
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if (trace)
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LogDebug("Rule Trace,\tRewriteDynTGRF from %s Slot=%u Dst=TG%u: matched", m_name.c_str(), m_slot, m_toTG);
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return RESULT_MATCHED;
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if (m_currentTG != 0U) {
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data.setDstId(m_currentTG);
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processMessage(data);
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return RESULT_MATCHED;
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} else {
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return RESULT_IGNORED;
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}
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}
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if (flco == FLCO_GROUP && std::find(m_exclTGs.cbegin(), m_exclTGs.cend(), dstId) != m_exclTGs.cend()) {
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if (trace)
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LogDebug("Rule Trace,\tRewriteDynTGRF from %s Slot=%u Dst=TG%u: not matched", m_name.c_str(), m_slot, dstId);
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return RESULT_UNMATCHED;
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}
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if (flco == FLCO_USER_USER && slotNo == m_slot && dstId == m_discPC && m_currentTG != 0U) {
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if (slotNo == m_slot && dstId == m_discPC) {
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if (trace)
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LogDebug("Rule Trace,\tRewriteDynTGRF from %s Slot=%u Dst=%u: matched", m_name.c_str(), m_slot, m_discPC);
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data.setFLCO(FLCO_GROUP);
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if (m_currentTG != 0U) {
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data.setFLCO(FLCO_GROUP);
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processMessage(data);
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processMessage(data);
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if (type == DT_TERMINATOR_WITH_LC) {
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m_rewriteNet->setCurrentTG(0U);
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m_currentTG = 0U;
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if (m_voice != NULL)
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m_voice->unlinked();
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if (type == DT_TERMINATOR_WITH_LC) {
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m_rewriteNet->setCurrentTG(0U);
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m_currentTG = 0U;
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if (m_voice != NULL)
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m_voice->unlinked();
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}
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return RESULT_MATCHED;
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} else {
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return RESULT_IGNORED;
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}
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return RESULT_MATCHED;
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}
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if (flco == FLCO_USER_USER && slotNo == m_slot && dstId >= m_fromTGStart && dstId <= m_fromTGEnd) {
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if (slotNo == m_slot && dstId == m_statusPC) {
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if (trace)
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LogDebug("Rule Trace,\tRewriteDynTGRF from %s Slot=%u Dst=%u: matched", m_name.c_str(), m_slot, m_statusPC);
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if (type == DT_TERMINATOR_WITH_LC && m_voice != NULL) {
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if (m_currentTG == 0U)
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m_voice->unlinked();
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else
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m_voice->linkedTo(m_currentTG);
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}
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return RESULT_IGNORED;
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}
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if (std::find(m_exclTGs.cbegin(), m_exclTGs.cend(), dstId) != m_exclTGs.cend()) {
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if (trace)
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LogDebug("Rule Trace,\tRewriteDynTGRF from %s Slot=%u Dst=%u: matched", m_name.c_str(), m_slot, dstId);
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return RESULT_IGNORED;
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}
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if (slotNo == m_slot && dstId >= m_fromTGStart && dstId <= m_fromTGEnd) {
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if (trace) {
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if (m_fromTGStart == m_fromTGEnd)
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LogDebug("Rule Trace,\tRewriteDynTGRF from %s Slot=%u Dst=%u: matched", m_name.c_str(), m_slot, m_fromTGStart);
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@@ -112,20 +134,6 @@ PROCESS_RESULT CRewriteDynTGRF::process(CDMRData& data, bool trace)
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return RESULT_MATCHED;
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}
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if (flco == FLCO_USER_USER && slotNo == m_slot && dstId == m_statusPC) {
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if (trace)
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LogDebug("Rule Trace,\tRewriteDynTGRF from %s Slot=%u Dst=%u: matched", m_name.c_str(), m_slot, m_statusPC);
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if (type == DT_TERMINATOR_WITH_LC && m_voice != NULL) {
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if (m_currentTG == 0U)
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m_voice->unlinked();
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else
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m_voice->linkedTo(m_currentTG);
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}
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return RESULT_IGNORED;
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}
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if (trace) {
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if (m_fromTGStart == m_fromTGEnd)
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LogDebug("Rule Trace,\tRewriteDynTGRF from %s Slot=%u Dst=%u or Dst=TG%u or Dst=%u or Dst=%u: not matched", m_name.c_str(), m_slot, m_fromTGStart, m_toTG, m_discPC, m_statusPC);
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