diff --git a/RewritePC.cpp b/RewritePC.cpp
index f3fb65a..2f76aea 100644
--- a/RewritePC.cpp
+++ b/RewritePC.cpp
@@ -32,6 +32,7 @@ m_fromIdStart(fromId),
 m_fromIdEnd(fromId + range - 1U),
 m_toSlot(toSlot),
 m_toIdStart(toId),
+m_toIdEnd(toId + range - 1U),
 m_trace(trace),
 m_lc(FLCO_USER_USER, 0U, 0U),
 m_embeddedLC()
@@ -49,7 +50,10 @@ bool CRewritePC::processRF(CDMRData& data)
 	bool ret = process(data);
 
 	if (m_trace)
-		LogDebug("Rule Trace,\tRewritePC %s Slot=%u Dst=%u-%u: %s", m_name, m_fromSlot, m_fromIdStart, m_fromIdEnd, ret ? "matched" : "not matched");
+		LogDebug("Rule Trace,\tRewritePC from %s Slot=%u Dst=%u-%u: %s", m_name, m_fromSlot, m_fromIdStart, m_fromIdEnd, ret ? "matched" : "not matched");
+		
+	if (m_trace && ret) 
+		LogDebug("Rule Trace,\tRewritePC to %s Slot=%u Dst=%u-%u", m_name, m_toSlot, m_toIdStart, m_toIdEnd);
 
 	return ret;
 }
@@ -59,7 +63,10 @@ bool CRewritePC::processNet(CDMRData& data)
 	bool ret = process(data);
 
 	if (m_trace)
-		LogDebug("Rule Trace,\tRewritePC %s Slot=%u Dst=%u-%u: %s", m_name, m_fromSlot, m_fromIdStart, m_fromIdEnd, ret ? "matched" : "not matched");
+		LogDebug("Rule Trace,\tRewritePC from %s Slot=%u Dst=%u-%u: %s", m_name, m_fromSlot, m_fromIdStart, m_fromIdEnd, ret ? "matched" : "not matched");
+		
+	if (m_trace && ret) 
+		LogDebug("Rule Trace,\tRewritePC to %s Slot=%u Dst=%u-%u", m_name, m_toSlot, m_toIdStart, m_toIdEnd);
 
 	return ret;
 }
diff --git a/RewritePC.h b/RewritePC.h
index d5872c3..0379a12 100644
--- a/RewritePC.h
+++ b/RewritePC.h
@@ -39,6 +39,7 @@ private:
 	unsigned int     m_fromIdEnd;
 	unsigned int     m_toSlot;
 	unsigned int     m_toIdStart;
+	unsigned int     m_toIdEnd;
 	bool             m_trace;
 	CDMRLC           m_lc;
 	CDMREmbeddedData m_embeddedLC;
diff --git a/RewriteSrc.cpp b/RewriteSrc.cpp
index 71541fc..e9c8f3e 100644
--- a/RewriteSrc.cpp
+++ b/RewriteSrc.cpp
@@ -51,7 +51,10 @@ bool CRewriteSrc::processRF(CDMRData& data)
 	bool ret = process(data);
 
 	if (m_trace)
-		LogDebug("Rule Trace,\tRewriteSrc %s Slot=%u Src=%u-%u: %s", m_name, m_fromSlot, m_fromIdStart, m_fromIdEnd, ret ? "matched" : "not matched");
+		LogDebug("Rule Trace,\tRewriteSrc from %s Slot=%u Src=%u-%u: %s", m_name, m_fromSlot, m_fromIdStart, m_fromIdEnd, ret ? "matched" : "not matched");
+		
+	if (m_trace && ret) 
+		LogDebug("Rule Trace,\tRewriteSrc to %s Slot=%u Dst=TG%u", m_name, m_toSlot, m_toTG);
 
 	return ret;
 }
@@ -61,7 +64,10 @@ bool CRewriteSrc::processNet(CDMRData& data)
 	bool ret = process(data);
 
 	if (m_trace)
-		LogDebug("Rule Trace,\tRewriteSrc %s Slot=%u Src=%u-%u: %s", m_name, m_fromSlot, m_fromIdStart, m_fromIdEnd, ret ? "matched" : "not matched");
+		LogDebug("Rule Trace,\tRewriteSrc from %s Slot=%u Src=%u-%u: %s", m_name, m_fromSlot, m_fromIdStart, m_fromIdEnd, ret ? "matched" : "not matched");
+		
+	if (m_trace && ret) 
+		LogDebug("Rule Trace,\tRewriteSrc to %s Slot=%u Dst=TG%u", m_name, m_toSlot, m_toTG);
 
 	return ret;
 }
diff --git a/RewriteTG.cpp b/RewriteTG.cpp
index 6c4cfac..63e3693 100644
--- a/RewriteTG.cpp
+++ b/RewriteTG.cpp
@@ -32,6 +32,7 @@ m_fromTGStart(fromTG),
 m_fromTGEnd(fromTG + range - 1U),
 m_toSlot(toSlot),
 m_toTGStart(toTG),
+m_toTGEnd(toTG + range - 1U),
 m_trace(trace),
 m_lc(FLCO_GROUP, 0U, toTG),
 m_embeddedLC()
@@ -49,7 +50,10 @@ bool CRewriteTG::processRF(CDMRData& data)
 	bool ret = process(data);
 
 	if (m_trace)
-		LogDebug("Rule Trace,\tRewriteTG %s Slot=%u Dst=TG%u-TG%u: %s", m_name, m_fromSlot, m_fromTGStart, m_fromTGEnd, ret ? "matched" : "not matched");
+		LogDebug("Rule Trace,\tRewriteTG from %s Slot=%u Dst=TG%u-TG%u: %s", m_name, m_fromSlot, m_fromTGStart, m_fromTGEnd, ret ? "matched" : "not matched");
+		
+	if (m_trace && ret) 
+		LogDebug("Rule Trace,\tRewriteTG to %s Slot=%u Dst=TG%u-TG%u", m_name, m_toSlot, m_toTGStart, m_toTGEnd);
 
 	return ret;
 }
@@ -59,7 +63,10 @@ bool CRewriteTG::processNet(CDMRData& data)
 	bool ret = process(data);
 
 	if (m_trace)
-		LogDebug("Rule Trace,\tRewriteTG %s Slot=%u Dst=TG%u-TG%u: %s", m_name, m_fromSlot, m_fromTGStart, m_fromTGEnd, ret ? "matched" : "not matched");
+		LogDebug("Rule Trace,\tRewriteTG from %s Slot=%u Dst=TG%u-TG%u: %s", m_name, m_fromSlot, m_fromTGStart, m_fromTGEnd, ret ? "matched" : "not matched");
+		
+	if (m_trace && ret) 
+		LogDebug("Rule Trace,\tRewriteTG to %s Slot=%u Dst=TG%u-TG%u", m_name, m_toSlot, m_toTGStart, m_toTGEnd);
 
 	return ret;
 }
diff --git a/RewriteTG.h b/RewriteTG.h
index 1b61799..3db2266 100644
--- a/RewriteTG.h
+++ b/RewriteTG.h
@@ -39,6 +39,7 @@ private:
 	unsigned int     m_fromTGEnd;
 	unsigned int     m_toSlot;
 	unsigned int     m_toTGStart;
+	unsigned int     m_toTGEnd;
 	bool             m_trace;
 	CDMRLC           m_lc;
 	CDMREmbeddedData m_embeddedLC;