mirror of
https://github.com/g4klx/DMRGateway
synced 2025-12-21 13:35:40 +08:00
Update the C++ code.
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@@ -1,5 +1,5 @@
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/*
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* Copyright (C) 2017,2020 by Jonathan Naylor G4KLX
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* Copyright (C) 2017,2020,2025 by Jonathan Naylor G4KLX
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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@@ -44,11 +44,11 @@ PROCESS_RESULT CRewriteDynTGNet::process(CDMRData& data, bool trace)
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unsigned int dstId = data.getDstId();
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unsigned int slotNo = data.getSlotNo();
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if (flco != FLCO_GROUP || slotNo != m_slot || dstId != m_currentTG) {
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if (flco != FLCO::GROUP || slotNo != m_slot || dstId != m_currentTG) {
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if (trace)
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LogDebug("Rule Trace,\tRewriteDynTGNet from %s Slot=%u Dst=TG%u: not matched", m_name.c_str(), m_slot, m_currentTG);
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return RESULT_UNMATCHED;
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return PROCESS_RESULT::UNMATCHED;
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}
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data.setDstId(m_toTG);
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@@ -58,7 +58,7 @@ PROCESS_RESULT CRewriteDynTGNet::process(CDMRData& data, bool trace)
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if (trace)
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LogDebug("Rule Trace,\tRewriteDynTGNet from %s Slot=%u Dst=TG%u: matched", m_name.c_str(), m_slot, m_currentTG);
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return RESULT_MATCHED;
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return PROCESS_RESULT::MATCHED;
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}
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void CRewriteDynTGNet::setCurrentTG(unsigned int currentTG)
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