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Add separate blacklist/whitelist for RF and NET

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This commit is contained in:
Simon
2016-07-10 21:37:11 +01:00
parent 8e6344f50c
commit 53fe88bf9e
9 changed files with 251 additions and 116 deletions
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167
DMRAccessControl.cpp
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@@ -19,10 +19,15 @@
#include <algorithm>
#include <vector>
std::vector<unsigned int> DMRAccessControl::m_dstBlackListSlot1;
std::vector<unsigned int> DMRAccessControl::m_dstBlackListSlot2;
std::vector<unsigned int> DMRAccessControl::m_dstWhiteListSlot1;
std::vector<unsigned int> DMRAccessControl::m_dstWhiteListSlot2;
std::vector<unsigned int> DMRAccessControl::m_dstBlackListSlot1RF;
std::vector<unsigned int> DMRAccessControl::m_dstBlackListSlot2RF;
std::vector<unsigned int> DMRAccessControl::m_dstWhiteListSlot1RF;
std::vector<unsigned int> DMRAccessControl::m_dstWhiteListSlot2RF;
std::vector<unsigned int> DMRAccessControl::m_dstBlackListSlot1NET;
std::vector<unsigned int> DMRAccessControl::m_dstBlackListSlot2NET;
std::vector<unsigned int> DMRAccessControl::m_dstWhiteListSlot1NET;
std::vector<unsigned int> DMRAccessControl::m_dstWhiteListSlot2NET;
std::vector<unsigned int> DMRAccessControl::m_SrcIdBlacklist;
@@ -30,66 +35,126 @@ std::vector<unsigned int> DMRAccessControl::m_prefixes;
bool DMRAccessControl::m_selfOnly;
unsigned int DMRAccessControl::m_id;
void DMRAccessControl::init(const std::vector<unsigned int>& DstIdBlacklistSlot1, const std::vector<unsigned int>& DstIdWhitelistSlot1, const std::vector<unsigned int>& DstIdBlacklistSlot2, const std::vector<unsigned int>& DstIdWhitelistSlot2, const std::vector<unsigned int>& SrcIdBlacklist, bool selfOnly, const std::vector<unsigned int>& prefixes,unsigned int id)
void DMRAccessControl::init(const std::vector<unsigned int>& DstIdBlacklistSlot1RF, const std::vector<unsigned int>& DstIdWhitelistSlot1RF, const std::vector<unsigned int>& DstIdBlacklistSlot2RF, const std::vector<unsigned int>& DstIdWhitelistSlot2RF, const std::vector<unsigned int>& DstIdBlacklistSlot1NET, const std::vector<unsigned int>& DstIdWhitelistSlot1NET, const std::vector<unsigned int>& DstIdBlacklistSlot2NET, const std::vector<unsigned int>& DstIdWhitelistSlot2NET, const std::vector<unsigned int>& SrcIdBlacklist, bool selfOnly, const std::vector<unsigned int>& prefixes,unsigned int id)
{
m_dstBlackListSlot1 = DstIdBlacklistSlot1;
m_dstWhiteListSlot1 = DstIdWhitelistSlot1;
m_dstBlackListSlot2 = DstIdBlacklistSlot2;
m_dstWhiteListSlot2 = DstIdWhitelistSlot2;
m_dstBlackListSlot1RF = DstIdBlacklistSlot1RF;
m_dstWhiteListSlot1RF = DstIdWhitelistSlot1RF;
m_dstBlackListSlot2RF = DstIdBlacklistSlot2RF;
m_dstWhiteListSlot2RF = DstIdWhitelistSlot2RF;
m_dstBlackListSlot1NET = DstIdBlacklistSlot1NET;
m_dstWhiteListSlot1NET = DstIdWhitelistSlot1NET;
m_dstBlackListSlot2NET = DstIdBlacklistSlot2NET;
m_dstWhiteListSlot2NET = DstIdWhitelistSlot2NET;
}
bool DMRAccessControl::DstIdBlacklist(unsigned int did, unsigned int slot)
bool DMRAccessControl::DstIdBlacklist(unsigned int did, unsigned int slot, bool network)
{
static std::vector<unsigned int> Blacklist;
if (slot == 1U) {
if (std::find(m_dstBlackListSlot1.begin(), m_dstBlackListSlot1.end(), did) != m_dstBlackListSlot1.end())
return true;
if (network) {
Blacklist = m_dstBlackListSlot1NET;
}
else {
Blacklist = m_dstBlackListSlot1RF;
}
} else {
if (std::find(m_dstBlackListSlot2.begin(), m_dstBlackListSlot2.end(), did) != m_dstBlackListSlot2.end())
return true;
if (network) {
Blacklist = m_dstBlackListSlot2NET;
}
else {
Blacklist = m_dstBlackListSlot2RF;
}
}
if (std::find(Blacklist.begin(), Blacklist.end(), did) != Blacklist.end())
return true;
return false;
}
bool DMRAccessControl::DstIdWhitelist(unsigned int did, unsigned int slot, bool gt4k)
bool DMRAccessControl::DstIdWhitelist(unsigned int did, unsigned int slot, bool gt4k, bool network)
{
if (slot == 1U) {
if (m_dstWhiteListSlot1.size() == 0U)
return true;
// No reflectors on slot1, so we only allow all IDs over 99999 unless specifically whitelisted.
//Allow traffic to TG0 as I think this is a special case - need to confirm
if (gt4k) {
if (std::find(m_dstWhiteListSlot1.begin(), m_dstWhiteListSlot1.end(), did) != m_dstWhiteListSlot1.end() || did >= 99999U || did == 0)
return true;
} else {
if (std::find(m_dstWhiteListSlot1.begin(), m_dstWhiteListSlot1.end(), did) != m_dstWhiteListSlot1.end() || did == 0)
return true;
}
} else {
if (m_dstWhiteListSlot2.size() == 0U)
return true;
//On slot2 we allow reflector control IDs, but not secondary TG IDs unless specifically listed. Also allow echo.
if (gt4k) {
if (std::find(m_dstWhiteListSlot2.begin(), m_dstWhiteListSlot2.end(), did) != m_dstWhiteListSlot2.end() || did == 0)
if (network) {
if (slot == 1U) {
if (m_dstWhiteListSlot1NET.size() == 0U)
return true;
//if dstId in secondary TG range or whitelist
else if (did >= 4000) {
if (did > 5000U && did < 10000U)
return false;
else
return true;
}
} else {
if (std::find(m_dstWhiteListSlot2.begin(), m_dstWhiteListSlot2.end(), did) != m_dstWhiteListSlot2.end())
return true;
}
}
return false;
// No reflectors on slot1, so we only allow all IDs over 99999 unless specifically whitelisted.
//Allow traffic to TG0 as I think this is a special case - need to confirm
if (gt4k) {
if (std::find(m_dstWhiteListSlot1NET.begin(), m_dstWhiteListSlot1NET.end(), did) != m_dstWhiteListSlot1NET.end() || did >= 99999U || did == 0)
return true;
} else {
if (std::find(m_dstWhiteListSlot1NET.begin(), m_dstWhiteListSlot1NET.end(), did) != m_dstWhiteListSlot1NET.end() || did == 0)
return true;
}
} else {
if (m_dstWhiteListSlot2NET.size() == 0U)
return true;
//On slot2 we allow reflector control IDs, but not secondary TG IDs unless specifically listed. Also allow echo.
if (gt4k) {
if (std::find(m_dstWhiteListSlot2NET.begin(), m_dstWhiteListSlot2NET.end(), did) != m_dstWhiteListSlot2NET.end() || did == 0)
return true;
//if dstId in secondary TG range or whitelist
else if (did >= 4000) {
if (did > 5000U && did < 10000U)
return false;
else
return true;
}
} else {
if (std::find(m_dstWhiteListSlot2NET.begin(), m_dstWhiteListSlot2NET.end(), did) != m_dstWhiteListSlot2NET.end())
return true;
}
}
return false;
} else {
if (slot == 1U) {
if (m_dstWhiteListSlot1RF.size() == 0U)
return true;
// No reflectors on slot1, so we only allow all IDs over 99999 unless specifically whitelisted.
//Allow traffic to TG0 as I think this is a special case - need to confirm
if (gt4k) {
if (std::find(m_dstWhiteListSlot1RF.begin(), m_dstWhiteListSlot1RF.end(), did) != m_dstWhiteListSlot1RF.end() || did >= 99999U || did == 0)
return true;
} else {
if (std::find(m_dstWhiteListSlot1RF.begin(), m_dstWhiteListSlot1RF.end(), did) != m_dstWhiteListSlot1RF.end() || did == 0)
return true;
}
} else {
if (m_dstWhiteListSlot2RF.size() == 0U)
return true;
//On slot2 we allow reflector control IDs, but not secondary TG IDs unless specifically listed. Also allow echo.
if (gt4k) {
if (std::find(m_dstWhiteListSlot2RF.begin(), m_dstWhiteListSlot2RF.end(), did) != m_dstWhiteListSlot2RF.end() || did == 0)
return true;
//if dstId in secondary TG range or whitelist
else if (did >= 4000) {
if (did > 5000U && did < 10000U)
return false;
else
return true;
}
} else {
if (std::find(m_dstWhiteListSlot2RF.begin(), m_dstWhiteListSlot2RF.end(), did) != m_dstWhiteListSlot2RF.end())
return true;
}
}
return false;
}
}
bool DMRAccessControl::validateSrcId(unsigned int id)
@@ -119,11 +184,11 @@ bool DMRAccessControl::validateAccess (unsigned int src_id, unsigned int dst_id,
return false;
}
else if (DMRAccessControl::DstIdBlacklist(dst_id, slot)) {
else if (DMRAccessControl::DstIdBlacklist(dst_id, slot, network)) {
LogMessage("DMR Slot %u, invalid access attempt to TG%u (TG blacklisted)", slot, dst_id);
return false;
}
else if (!DMRAccessControl::DstIdWhitelist(dst_id, slot, true)) {
else if (!DMRAccessControl::DstIdWhitelist(dst_id, slot, true, network)) {
LogMessage("DMR Slot %u, invalid access attempt to TG%u (TG not in whitelist)", slot, dst_id);
return false;
}