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https://github.com/g4klx/MMDVMHost
synced 2025-12-23 16:55:52 +08:00
Clean up TG rewrite code.
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@@ -296,8 +296,8 @@ int CMMDVMHost::run()
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unsigned int id = m_conf.getDMRId();
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unsigned int colorCode = m_conf.getDMRColorCode();
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bool selfOnly = m_conf.getDMRSelfOnly();
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bool TGRewriteSlot1 = m_conf.getDMRTGRewriteSlot1();
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bool TGRewriteSlot2 = m_conf.getDMRTGRewriteSlot2();
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bool tgRewriteSlot1 = m_conf.getDMRTGRewriteSlot1();
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bool tgRewriteSlot2 = m_conf.getDMRTGRewriteSlot2();
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std::vector<unsigned int> prefixes = m_conf.getDMRPrefixes();
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std::vector<unsigned int> blackList = m_conf.getDMRBlackList();
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std::vector<unsigned int> dstIDBlackListSlot1RF = m_conf.getDMRDstIdBlacklistSlot1RF();
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@@ -356,15 +356,14 @@ int CMMDVMHost::run()
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LogInfo(" RSSI Multiplier: %d", rssiMultiplier);
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LogInfo(" RSSI Offset: %d", rssiOffset);
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}
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if (TGRewriteSlot1)
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LogInfo(" TG Rewrite Slot 1 enabled");
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if (TGRewriteSlot2)
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LogInfo(" TG Rewrite Slot 2 enabled");
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dmr = new CDMRControl(id, colorCode, callHang, selfOnly, prefixes, blackList,dstIDBlackListSlot1RF,dstIDWhiteListSlot1RF, dstIDBlackListSlot2RF, dstIDWhiteListSlot2RF, dstIDBlackListSlot1NET,dstIDWhiteListSlot1NET, dstIDBlackListSlot2NET, dstIDWhiteListSlot2NET, m_timeout, m_modem, m_dmrNetwork, m_display, m_duplex, lookupFile, rssiMultiplier, rssiOffset, jitter, TGRewriteSlot1, TGRewriteSlot2);
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if (tgRewriteSlot1)
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LogInfo(" TG Rewrite Slot 1 enabled");
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if (tgRewriteSlot2)
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LogInfo(" TG Rewrite Slot 2 enabled");
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dmr = new CDMRControl(id, colorCode, callHang, selfOnly, prefixes, blackList,dstIDBlackListSlot1RF,dstIDWhiteListSlot1RF, dstIDBlackListSlot2RF, dstIDWhiteListSlot2RF, dstIDBlackListSlot1NET,dstIDWhiteListSlot1NET, dstIDBlackListSlot2NET, dstIDWhiteListSlot2NET, m_timeout, m_modem, m_dmrNetwork, m_display, m_duplex, lookupFile, rssiMultiplier, rssiOffset, jitter, tgRewriteSlot1, tgRewriteSlot2);
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m_dmrTXTimer.setTimeout(txHang);
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}
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