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Begin the dynamic TG support.

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This commit is contained in:
Jonathan Naylor
2020-04-01 22:22:12 +01:00
parent 0014432195
commit 10e890bdd4
11 changed files with 539 additions and 76 deletions
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107
Conf.cpp
View File

@@ -1,5 +1,5 @@
/*
* Copyright (C) 2015-2019 by Jonathan Naylor G4KLX
* Copyright (C) 2015-2020 by Jonathan Naylor G4KLX
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -82,6 +82,7 @@ m_dmrNetwork1TGRewrites(),
m_dmrNetwork1PCRewrites(),
m_dmrNetwork1TypeRewrites(),
m_dmrNetwork1SrcRewrites(),
m_dmrNetwork1TGDynRewrites(),
m_dmrNetwork1IdRewrites(),
m_dmrNetwork1PassAllPC(),
m_dmrNetwork1PassAllTG(),
@@ -99,6 +100,7 @@ m_dmrNetwork2TGRewrites(),
m_dmrNetwork2PCRewrites(),
m_dmrNetwork2TypeRewrites(),
m_dmrNetwork2SrcRewrites(),
m_dmrNetwork2TGDynRewrites(),
m_dmrNetwork2IdRewrites(),
m_dmrNetwork2PassAllPC(),
m_dmrNetwork2PassAllTG(),
@@ -116,6 +118,7 @@ m_dmrNetwork3TGRewrites(),
m_dmrNetwork3PCRewrites(),
m_dmrNetwork3TypeRewrites(),
m_dmrNetwork3SrcRewrites(),
m_dmrNetwork3TGDynRewrites(),
m_dmrNetwork3IdRewrites(),
m_dmrNetwork3PassAllPC(),
m_dmrNetwork3PassAllTG(),
@@ -133,6 +136,7 @@ m_dmrNetwork4TGRewrites(),
m_dmrNetwork4PCRewrites(),
m_dmrNetwork4TypeRewrites(),
m_dmrNetwork4SrcRewrites(),
m_dmrNetwork4TGDynRewrites(),
m_dmrNetwork4IdRewrites(),
m_dmrNetwork4PassAllPC(),
m_dmrNetwork4PassAllTG(),
@@ -150,6 +154,7 @@ m_dmrNetwork5TGRewrites(),
m_dmrNetwork5PCRewrites(),
m_dmrNetwork5TypeRewrites(),
m_dmrNetwork5SrcRewrites(),
m_dmrNetwork5TGDynRewrites(),
m_dmrNetwork5IdRewrites(),
m_dmrNetwork5PassAllPC(),
m_dmrNetwork5PassAllTG(),
@@ -400,6 +405,21 @@ bool CConf::read()
rewrite.m_range = ::atoi(p5);
m_dmrNetwork1SrcRewrites.push_back(rewrite);
}
} else if (::strncmp(key, "TGDynRewrite", 12U) == 0) {
char* p1 = ::strtok(value, ", ");
char* p2 = ::strtok(NULL, ", ");
char* p3 = ::strtok(NULL, ", ");
char* p4 = ::strtok(NULL, " \r\n");
char* p5 = ::strtok(NULL, " \r\n");
if (p1 != NULL && p2 != NULL && p3 != NULL && p4 != NULL && p5 != NULL) {
CTGDynRewriteStruct rewrite;
rewrite.m_slot = ::atoi(p1);
rewrite.m_fromTG = ::atoi(p2);
rewrite.m_discTG = ::atoi(p3);
rewrite.m_toTG = ::atoi(p4);
rewrite.m_range = ::atoi(p5);
m_dmrNetwork1TGDynRewrites.push_back(rewrite);
}
} else if (::strncmp(key, "IdRewrite", 9U) == 0) {
char* rfId = ::strtok(value, ", ");
char* netId = ::strtok(NULL, " \r\n");
@@ -495,6 +515,21 @@ bool CConf::read()
rewrite.m_range = ::atoi(p5);
m_dmrNetwork2SrcRewrites.push_back(rewrite);
}
} else if (::strncmp(key, "TGDynRewrite", 12U) == 0) {
char* p1 = ::strtok(value, ", ");
char* p2 = ::strtok(NULL, ", ");
char* p3 = ::strtok(NULL, ", ");
char* p4 = ::strtok(NULL, " \r\n");
char* p5 = ::strtok(NULL, " \r\n");
if (p1 != NULL && p2 != NULL && p3 != NULL && p4 != NULL && p5 != NULL) {
CTGDynRewriteStruct rewrite;
rewrite.m_slot = ::atoi(p1);
rewrite.m_fromTG = ::atoi(p2);
rewrite.m_discTG = ::atoi(p3);
rewrite.m_toTG = ::atoi(p4);
rewrite.m_range = ::atoi(p5);
m_dmrNetwork2TGDynRewrites.push_back(rewrite);
}
} else if (::strncmp(key, "IdRewrite", 9U) == 0) {
char* rfId = ::strtok(value, ", ");
char* netId = ::strtok(NULL, " \r\n");
@@ -590,6 +625,21 @@ bool CConf::read()
rewrite.m_range = ::atoi(p5);
m_dmrNetwork3SrcRewrites.push_back(rewrite);
}
} else if (::strncmp(key, "TGDynRewrite", 12U) == 0) {
char* p1 = ::strtok(value, ", ");
char* p2 = ::strtok(NULL, ", ");
char* p3 = ::strtok(NULL, ", ");
char* p4 = ::strtok(NULL, " \r\n");
char* p5 = ::strtok(NULL, " \r\n");
if (p1 != NULL && p2 != NULL && p3 != NULL && p4 != NULL && p5 != NULL) {
CTGDynRewriteStruct rewrite;
rewrite.m_slot = ::atoi(p1);
rewrite.m_fromTG = ::atoi(p2);
rewrite.m_discTG = ::atoi(p3);
rewrite.m_toTG = ::atoi(p4);
rewrite.m_range = ::atoi(p5);
m_dmrNetwork3TGDynRewrites.push_back(rewrite);
}
} else if (::strncmp(key, "IdRewrite", 9U) == 0) {
char* rfId = ::strtok(value, ", ");
char* netId = ::strtok(NULL, " \r\n");
@@ -685,6 +735,21 @@ bool CConf::read()
rewrite.m_range = ::atoi(p5);
m_dmrNetwork4SrcRewrites.push_back(rewrite);
}
} else if (::strncmp(key, "TGDynRewrite", 12U) == 0) {
char* p1 = ::strtok(value, ", ");
char* p2 = ::strtok(NULL, ", ");
char* p3 = ::strtok(NULL, ", ");
char* p4 = ::strtok(NULL, " \r\n");
char* p5 = ::strtok(NULL, " \r\n");
if (p1 != NULL && p2 != NULL && p3 != NULL && p4 != NULL && p5 != NULL) {
CTGDynRewriteStruct rewrite;
rewrite.m_slot = ::atoi(p1);
rewrite.m_fromTG = ::atoi(p2);
rewrite.m_discTG = ::atoi(p3);
rewrite.m_toTG = ::atoi(p4);
rewrite.m_range = ::atoi(p5);
m_dmrNetwork4TGDynRewrites.push_back(rewrite);
}
} else if (::strncmp(key, "IdRewrite", 9U) == 0) {
char* rfId = ::strtok(value, ", ");
char* netId = ::strtok(NULL, " \r\n");
@@ -780,6 +845,21 @@ bool CConf::read()
rewrite.m_range = ::atoi(p5);
m_dmrNetwork5SrcRewrites.push_back(rewrite);
}
} else if (::strncmp(key, "TGDynRewrite", 12U) == 0) {
char* p1 = ::strtok(value, ", ");
char* p2 = ::strtok(NULL, ", ");
char* p3 = ::strtok(NULL, ", ");
char* p4 = ::strtok(NULL, " \r\n");
char* p5 = ::strtok(NULL, " \r\n");
if (p1 != NULL && p2 != NULL && p3 != NULL && p4 != NULL && p5 != NULL) {
CTGDynRewriteStruct rewrite;
rewrite.m_slot = ::atoi(p1);
rewrite.m_fromTG = ::atoi(p2);
rewrite.m_discTG = ::atoi(p3);
rewrite.m_toTG = ::atoi(p4);
rewrite.m_range = ::atoi(p5);
m_dmrNetwork5TGDynRewrites.push_back(rewrite);
}
} else if (::strncmp(key, "IdRewrite", 9U) == 0) {
char* rfId = ::strtok(value, ", ");
char* netId = ::strtok(NULL, " \r\n");
@@ -1080,6 +1160,11 @@ std::vector<CSrcRewriteStruct> CConf::getDMRNetwork1SrcRewrites() const
return m_dmrNetwork1SrcRewrites;
}
std::vector<CTGDynRewriteStruct> CConf::getDMRNetwork1TGDynRewrites() const
{
return m_dmrNetwork1TGDynRewrites;
}
std::vector<CIdRewriteStruct> CConf::getDMRNetwork1IdRewrites() const
{
return m_dmrNetwork1IdRewrites;
@@ -1168,6 +1253,11 @@ std::vector<CSrcRewriteStruct> CConf::getDMRNetwork2SrcRewrites() const
return m_dmrNetwork2SrcRewrites;
}
std::vector<CTGDynRewriteStruct> CConf::getDMRNetwork2TGDynRewrites() const
{
return m_dmrNetwork2TGDynRewrites;
}
std::vector<CIdRewriteStruct> CConf::getDMRNetwork2IdRewrites() const
{
return m_dmrNetwork2IdRewrites;
@@ -1256,6 +1346,11 @@ std::vector<CSrcRewriteStruct> CConf::getDMRNetwork3SrcRewrites() const
return m_dmrNetwork3SrcRewrites;
}
std::vector<CTGDynRewriteStruct> CConf::getDMRNetwork3TGDynRewrites() const
{
return m_dmrNetwork3TGDynRewrites;
}
std::vector<CIdRewriteStruct> CConf::getDMRNetwork3IdRewrites() const
{
return m_dmrNetwork3IdRewrites;
@@ -1344,6 +1439,11 @@ std::vector<CSrcRewriteStruct> CConf::getDMRNetwork4SrcRewrites() const
return m_dmrNetwork4SrcRewrites;
}
std::vector<CTGDynRewriteStruct> CConf::getDMRNetwork4TGDynRewrites() const
{
return m_dmrNetwork4TGDynRewrites;
}
std::vector<CIdRewriteStruct> CConf::getDMRNetwork4IdRewrites() const
{
return m_dmrNetwork4IdRewrites;
@@ -1432,6 +1532,11 @@ std::vector<CSrcRewriteStruct> CConf::getDMRNetwork5SrcRewrites() const
return m_dmrNetwork5SrcRewrites;
}
std::vector<CTGDynRewriteStruct> CConf::getDMRNetwork5TGDynRewrites() const
{
return m_dmrNetwork5TGDynRewrites;
}
std::vector<CIdRewriteStruct> CConf::getDMRNetwork5IdRewrites() const
{
return m_dmrNetwork5IdRewrites;

160
Conf.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (C) 2015,2016,2017,2019 by Jonathan Naylor G4KLX
* Copyright (C) 2015,2016,2017,2019,2020 by Jonathan Naylor G4KLX
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -53,6 +53,14 @@ struct CSrcRewriteStruct {
unsigned int m_range;
};
struct CTGDynRewriteStruct {
unsigned int m_slot;
unsigned int m_fromTG;
unsigned int m_discTG;
unsigned int m_toTG;
unsigned int m_range;
};
struct CIdRewriteStruct {
unsigned int m_rfId;
unsigned int m_netId;
@@ -111,13 +119,14 @@ public:
std::string getDMRNetwork1Options() const;
bool getDMRNetwork1Location() const;
bool getDMRNetwork1Debug() const;
std::vector<CTGRewriteStruct> getDMRNetwork1TGRewrites() const;
std::vector<CPCRewriteStruct> getDMRNetwork1PCRewrites() const;
std::vector<CTypeRewriteStruct> getDMRNetwork1TypeRewrites() const;
std::vector<CSrcRewriteStruct> getDMRNetwork1SrcRewrites() const;
std::vector<CIdRewriteStruct> getDMRNetwork1IdRewrites() const;
std::vector<unsigned int> getDMRNetwork1PassAllPC() const;
std::vector<unsigned int> getDMRNetwork1PassAllTG() const;
std::vector<CTGRewriteStruct> getDMRNetwork1TGRewrites() const;
std::vector<CPCRewriteStruct> getDMRNetwork1PCRewrites() const;
std::vector<CTypeRewriteStruct> getDMRNetwork1TypeRewrites() const;
std::vector<CSrcRewriteStruct> getDMRNetwork1SrcRewrites() const;
std::vector<CTGDynRewriteStruct> getDMRNetwork1TGDynRewrites() const;
std::vector<CIdRewriteStruct> getDMRNetwork1IdRewrites() const;
std::vector<unsigned int> getDMRNetwork1PassAllPC() const;
std::vector<unsigned int> getDMRNetwork1PassAllTG() const;
// The DMR Network 2 section
bool getDMRNetwork2Enabled() const;
@@ -130,13 +139,14 @@ public:
std::string getDMRNetwork2Options() const;
bool getDMRNetwork2Location() const;
bool getDMRNetwork2Debug() const;
std::vector<CTGRewriteStruct> getDMRNetwork2TGRewrites() const;
std::vector<CPCRewriteStruct> getDMRNetwork2PCRewrites() const;
std::vector<CTypeRewriteStruct> getDMRNetwork2TypeRewrites() const;
std::vector<CSrcRewriteStruct> getDMRNetwork2SrcRewrites() const;
std::vector<CIdRewriteStruct> getDMRNetwork2IdRewrites() const;
std::vector<unsigned int> getDMRNetwork2PassAllPC() const;
std::vector<unsigned int> getDMRNetwork2PassAllTG() const;
std::vector<CTGRewriteStruct> getDMRNetwork2TGRewrites() const;
std::vector<CPCRewriteStruct> getDMRNetwork2PCRewrites() const;
std::vector<CTypeRewriteStruct> getDMRNetwork2TypeRewrites() const;
std::vector<CSrcRewriteStruct> getDMRNetwork2SrcRewrites() const;
std::vector<CTGDynRewriteStruct> getDMRNetwork2TGDynRewrites() const;
std::vector<CIdRewriteStruct> getDMRNetwork2IdRewrites() const;
std::vector<unsigned int> getDMRNetwork2PassAllPC() const;
std::vector<unsigned int> getDMRNetwork2PassAllTG() const;
// The DMR Network 3 section
bool getDMRNetwork3Enabled() const;
@@ -149,13 +159,14 @@ public:
std::string getDMRNetwork3Options() const;
bool getDMRNetwork3Location() const;
bool getDMRNetwork3Debug() const;
std::vector<CTGRewriteStruct> getDMRNetwork3TGRewrites() const;
std::vector<CPCRewriteStruct> getDMRNetwork3PCRewrites() const;
std::vector<CTypeRewriteStruct> getDMRNetwork3TypeRewrites() const;
std::vector<CSrcRewriteStruct> getDMRNetwork3SrcRewrites() const;
std::vector<CIdRewriteStruct> getDMRNetwork3IdRewrites() const;
std::vector<unsigned int> getDMRNetwork3PassAllPC() const;
std::vector<unsigned int> getDMRNetwork3PassAllTG() const;
std::vector<CTGRewriteStruct> getDMRNetwork3TGRewrites() const;
std::vector<CPCRewriteStruct> getDMRNetwork3PCRewrites() const;
std::vector<CTypeRewriteStruct> getDMRNetwork3TypeRewrites() const;
std::vector<CSrcRewriteStruct> getDMRNetwork3SrcRewrites() const;
std::vector<CTGDynRewriteStruct> getDMRNetwork3TGDynRewrites() const;
std::vector<CIdRewriteStruct> getDMRNetwork3IdRewrites() const;
std::vector<unsigned int> getDMRNetwork3PassAllPC() const;
std::vector<unsigned int> getDMRNetwork3PassAllTG() const;
// The DMR Network 4 section
bool getDMRNetwork4Enabled() const;
@@ -168,13 +179,14 @@ public:
std::string getDMRNetwork4Options() const;
bool getDMRNetwork4Location() const;
bool getDMRNetwork4Debug() const;
std::vector<CTGRewriteStruct> getDMRNetwork4TGRewrites() const;
std::vector<CPCRewriteStruct> getDMRNetwork4PCRewrites() const;
std::vector<CTypeRewriteStruct> getDMRNetwork4TypeRewrites() const;
std::vector<CSrcRewriteStruct> getDMRNetwork4SrcRewrites() const;
std::vector<CIdRewriteStruct> getDMRNetwork4IdRewrites() const;
std::vector<unsigned int> getDMRNetwork4PassAllPC() const;
std::vector<unsigned int> getDMRNetwork4PassAllTG() const;
std::vector<CTGRewriteStruct> getDMRNetwork4TGRewrites() const;
std::vector<CPCRewriteStruct> getDMRNetwork4PCRewrites() const;
std::vector<CTypeRewriteStruct> getDMRNetwork4TypeRewrites() const;
std::vector<CSrcRewriteStruct> getDMRNetwork4SrcRewrites() const;
std::vector<CTGDynRewriteStruct> getDMRNetwork4TGDynRewrites() const;
std::vector<CIdRewriteStruct> getDMRNetwork4IdRewrites() const;
std::vector<unsigned int> getDMRNetwork4PassAllPC() const;
std::vector<unsigned int> getDMRNetwork4PassAllTG() const;
// The DMR Network 5 section
bool getDMRNetwork5Enabled() const;
@@ -187,13 +199,14 @@ public:
std::string getDMRNetwork5Options() const;
bool getDMRNetwork5Location() const;
bool getDMRNetwork5Debug() const;
std::vector<CTGRewriteStruct> getDMRNetwork5TGRewrites() const;
std::vector<CPCRewriteStruct> getDMRNetwork5PCRewrites() const;
std::vector<CTypeRewriteStruct> getDMRNetwork5TypeRewrites() const;
std::vector<CSrcRewriteStruct> getDMRNetwork5SrcRewrites() const;
std::vector<CIdRewriteStruct> getDMRNetwork5IdRewrites() const;
std::vector<unsigned int> getDMRNetwork5PassAllPC() const;
std::vector<unsigned int> getDMRNetwork5PassAllTG() const;
std::vector<CTGRewriteStruct> getDMRNetwork5TGRewrites() const;
std::vector<CPCRewriteStruct> getDMRNetwork5PCRewrites() const;
std::vector<CTypeRewriteStruct> getDMRNetwork5TypeRewrites() const;
std::vector<CSrcRewriteStruct> getDMRNetwork5SrcRewrites() const;
std::vector<CTGDynRewriteStruct> getDMRNetwork5TGDynRewrites() const;
std::vector<CIdRewriteStruct> getDMRNetwork5IdRewrites() const;
std::vector<unsigned int> getDMRNetwork5PassAllPC() const;
std::vector<unsigned int> getDMRNetwork5PassAllTG() const;
// The XLX Network section
bool getXLXNetworkEnabled() const;
@@ -254,13 +267,14 @@ private:
std::string m_dmrNetwork1Options;
bool m_dmrNetwork1Location;
bool m_dmrNetwork1Debug;
std::vector<CTGRewriteStruct> m_dmrNetwork1TGRewrites;
std::vector<CPCRewriteStruct> m_dmrNetwork1PCRewrites;
std::vector<CTypeRewriteStruct> m_dmrNetwork1TypeRewrites;
std::vector<CSrcRewriteStruct> m_dmrNetwork1SrcRewrites;
std::vector<CIdRewriteStruct> m_dmrNetwork1IdRewrites;
std::vector<unsigned int> m_dmrNetwork1PassAllPC;
std::vector<unsigned int> m_dmrNetwork1PassAllTG;
std::vector<CTGRewriteStruct> m_dmrNetwork1TGRewrites;
std::vector<CPCRewriteStruct> m_dmrNetwork1PCRewrites;
std::vector<CTypeRewriteStruct> m_dmrNetwork1TypeRewrites;
std::vector<CSrcRewriteStruct> m_dmrNetwork1SrcRewrites;
std::vector<CTGDynRewriteStruct> m_dmrNetwork1TGDynRewrites;
std::vector<CIdRewriteStruct> m_dmrNetwork1IdRewrites;
std::vector<unsigned int> m_dmrNetwork1PassAllPC;
std::vector<unsigned int> m_dmrNetwork1PassAllTG;
bool m_dmrNetwork2Enabled;
std::string m_dmrNetwork2Name;
@@ -272,13 +286,14 @@ private:
std::string m_dmrNetwork2Options;
bool m_dmrNetwork2Location;
bool m_dmrNetwork2Debug;
std::vector<CTGRewriteStruct> m_dmrNetwork2TGRewrites;
std::vector<CPCRewriteStruct> m_dmrNetwork2PCRewrites;
std::vector<CTypeRewriteStruct> m_dmrNetwork2TypeRewrites;
std::vector<CSrcRewriteStruct> m_dmrNetwork2SrcRewrites;
std::vector<CIdRewriteStruct> m_dmrNetwork2IdRewrites;
std::vector<unsigned int> m_dmrNetwork2PassAllPC;
std::vector<unsigned int> m_dmrNetwork2PassAllTG;
std::vector<CTGRewriteStruct> m_dmrNetwork2TGRewrites;
std::vector<CPCRewriteStruct> m_dmrNetwork2PCRewrites;
std::vector<CTypeRewriteStruct> m_dmrNetwork2TypeRewrites;
std::vector<CSrcRewriteStruct> m_dmrNetwork2SrcRewrites;
std::vector<CTGDynRewriteStruct> m_dmrNetwork2TGDynRewrites;
std::vector<CIdRewriteStruct> m_dmrNetwork2IdRewrites;
std::vector<unsigned int> m_dmrNetwork2PassAllPC;
std::vector<unsigned int> m_dmrNetwork2PassAllTG;
bool m_dmrNetwork3Enabled;
std::string m_dmrNetwork3Name;
@@ -290,13 +305,14 @@ private:
std::string m_dmrNetwork3Options;
bool m_dmrNetwork3Location;
bool m_dmrNetwork3Debug;
std::vector<CTGRewriteStruct> m_dmrNetwork3TGRewrites;
std::vector<CPCRewriteStruct> m_dmrNetwork3PCRewrites;
std::vector<CTypeRewriteStruct> m_dmrNetwork3TypeRewrites;
std::vector<CSrcRewriteStruct> m_dmrNetwork3SrcRewrites;
std::vector<CIdRewriteStruct> m_dmrNetwork3IdRewrites;
std::vector<unsigned int> m_dmrNetwork3PassAllPC;
std::vector<unsigned int> m_dmrNetwork3PassAllTG;
std::vector<CTGRewriteStruct> m_dmrNetwork3TGRewrites;
std::vector<CPCRewriteStruct> m_dmrNetwork3PCRewrites;
std::vector<CTypeRewriteStruct> m_dmrNetwork3TypeRewrites;
std::vector<CSrcRewriteStruct> m_dmrNetwork3SrcRewrites;
std::vector<CTGDynRewriteStruct> m_dmrNetwork3TGDynRewrites;
std::vector<CIdRewriteStruct> m_dmrNetwork3IdRewrites;
std::vector<unsigned int> m_dmrNetwork3PassAllPC;
std::vector<unsigned int> m_dmrNetwork3PassAllTG;
bool m_dmrNetwork4Enabled;
std::string m_dmrNetwork4Name;
@@ -308,13 +324,14 @@ private:
std::string m_dmrNetwork4Options;
bool m_dmrNetwork4Location;
bool m_dmrNetwork4Debug;
std::vector<CTGRewriteStruct> m_dmrNetwork4TGRewrites;
std::vector<CPCRewriteStruct> m_dmrNetwork4PCRewrites;
std::vector<CTypeRewriteStruct> m_dmrNetwork4TypeRewrites;
std::vector<CSrcRewriteStruct> m_dmrNetwork4SrcRewrites;
std::vector<CIdRewriteStruct> m_dmrNetwork4IdRewrites;
std::vector<unsigned int> m_dmrNetwork4PassAllPC;
std::vector<unsigned int> m_dmrNetwork4PassAllTG;
std::vector<CTGRewriteStruct> m_dmrNetwork4TGRewrites;
std::vector<CPCRewriteStruct> m_dmrNetwork4PCRewrites;
std::vector<CTypeRewriteStruct> m_dmrNetwork4TypeRewrites;
std::vector<CSrcRewriteStruct> m_dmrNetwork4SrcRewrites;
std::vector<CTGDynRewriteStruct> m_dmrNetwork4TGDynRewrites;
std::vector<CIdRewriteStruct> m_dmrNetwork4IdRewrites;
std::vector<unsigned int> m_dmrNetwork4PassAllPC;
std::vector<unsigned int> m_dmrNetwork4PassAllTG;
bool m_dmrNetwork5Enabled;
std::string m_dmrNetwork5Name;
@@ -326,13 +343,14 @@ private:
std::string m_dmrNetwork5Options;
bool m_dmrNetwork5Location;
bool m_dmrNetwork5Debug;
std::vector<CTGRewriteStruct> m_dmrNetwork5TGRewrites;
std::vector<CPCRewriteStruct> m_dmrNetwork5PCRewrites;
std::vector<CTypeRewriteStruct> m_dmrNetwork5TypeRewrites;
std::vector<CSrcRewriteStruct> m_dmrNetwork5SrcRewrites;
std::vector<CIdRewriteStruct> m_dmrNetwork5IdRewrites;
std::vector<unsigned int> m_dmrNetwork5PassAllPC;
std::vector<unsigned int> m_dmrNetwork5PassAllTG;
std::vector<CTGRewriteStruct> m_dmrNetwork5TGRewrites;
std::vector<CPCRewriteStruct> m_dmrNetwork5PCRewrites;
std::vector<CTypeRewriteStruct> m_dmrNetwork5TypeRewrites;
std::vector<CSrcRewriteStruct> m_dmrNetwork5SrcRewrites;
std::vector<CTGDynRewriteStruct> m_dmrNetwork5TGDynRewrites;
std::vector<CIdRewriteStruct> m_dmrNetwork5IdRewrites;
std::vector<unsigned int> m_dmrNetwork5PassAllPC;
std::vector<unsigned int> m_dmrNetwork5PassAllTG;
bool m_xlxNetworkEnabled;
unsigned int m_xlxNetworkId;

61
DMRGateway.cpp
View File

@@ -1,5 +1,5 @@
/*
* Copyright (C) 2015-2019 by Jonathan Naylor G4KLX
* Copyright (C) 2015-2020 by Jonathan Naylor G4KLX
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -24,6 +24,8 @@
#include "RewritePC.h"
#include "RewriteSrcId.h"
#include "RewriteDstId.h"
#include "RewriteDynTGNet.h"
#include "RewriteDynTGRF.h"
#include "PassAllPC.h"
#include "PassAllTG.h"
#include "DMRFullLC.h"
@@ -71,7 +73,7 @@ static void sigHandler(int signum)
const char* HEADER1 = "This software is for use on amateur radio networks only,";
const char* HEADER2 = "it is to be used for educational purposes only. Its use on";
const char* HEADER3 = "commercial networks is strictly prohibited.";
const char* HEADER4 = "Copyright(C) 2017 by Jonathan Naylor, G4KLX and others";
const char* HEADER4 = "Copyright(C) 2017-2020 by Jonathan Naylor, G4KLX and others";
int main(int argc, char** argv)
{
@@ -1333,6 +1335,17 @@ bool CDMRGateway::createDMRNetwork1()
m_dmr1NetRewrites.push_back(rewrite);
}
std::vector<CTGDynRewriteStruct> dynRewrites = m_conf.getDMRNetwork1TGDynRewrites();
for (std::vector<CTGDynRewriteStruct>::const_iterator it = dynRewrites.begin(); it != dynRewrites.end(); ++it) {
LogInfo(" Dyn Rewrite: %u:TG%u-%u:TG%u <-> %u:TG%u (disc %u:TG%u)", (*it).m_slot, (*it).m_fromTG, (*it).m_slot, (*it).m_fromTG + (*it).m_range - 1U, (*it).m_slot, (*it).m_toTG, (*it).m_slot, (*it).m_discTG);
CRewriteDynTGNet* netRewriteDynTG = new CRewriteDynTGNet(m_dmr1Name, (*it).m_slot, (*it).m_fromTG, (*it).m_toTG, (*it).m_discTG, (*it).m_range);
CRewriteDynTGRF* rfRewriteDynTG = new CRewriteDynTGRF(m_dmr1Name, (*it).m_slot, (*it).m_fromTG, (*it).m_toTG, (*it).m_discTG, (*it).m_range, netRewriteDynTG);
m_dmr1RFRewrites.push_back(rfRewriteDynTG);
m_dmr1NetRewrites.push_back(netRewriteDynTG);
}
std::vector<CIdRewriteStruct> idRewrites = m_conf.getDMRNetwork1IdRewrites();
for (std::vector<CIdRewriteStruct>::const_iterator it = idRewrites.begin(); it != idRewrites.end(); ++it) {
LogInfo(" Rewrite Id: %u <-> %u", (*it).m_rfId, (*it).m_netId);
@@ -1471,6 +1484,17 @@ bool CDMRGateway::createDMRNetwork2()
m_dmr2NetRewrites.push_back(rewrite);
}
std::vector<CTGDynRewriteStruct> dynRewrites = m_conf.getDMRNetwork2TGDynRewrites();
for (std::vector<CTGDynRewriteStruct>::const_iterator it = dynRewrites.begin(); it != dynRewrites.end(); ++it) {
LogInfo(" Dyn Rewrite: %u:TG%u-%u:TG%u <-> %u:TG%u (disc %u:TG%u)", (*it).m_slot, (*it).m_fromTG, (*it).m_slot, (*it).m_fromTG + (*it).m_range - 1U, (*it).m_slot, (*it).m_toTG, (*it).m_slot, (*it).m_discTG);
CRewriteDynTGNet* netRewriteDynTG = new CRewriteDynTGNet(m_dmr2Name, (*it).m_slot, (*it).m_fromTG, (*it).m_toTG, (*it).m_discTG, (*it).m_range);
CRewriteDynTGRF* rfRewriteDynTG = new CRewriteDynTGRF(m_dmr2Name, (*it).m_slot, (*it).m_fromTG, (*it).m_toTG, (*it).m_discTG, (*it).m_range, netRewriteDynTG);
m_dmr2RFRewrites.push_back(rfRewriteDynTG);
m_dmr2NetRewrites.push_back(netRewriteDynTG);
}
std::vector<CIdRewriteStruct> idRewrites = m_conf.getDMRNetwork2IdRewrites();
for (std::vector<CIdRewriteStruct>::const_iterator it = idRewrites.begin(); it != idRewrites.end(); ++it) {
LogInfo(" Rewrite Id: %u <-> %u", (*it).m_rfId, (*it).m_netId);
@@ -1609,6 +1633,17 @@ bool CDMRGateway::createDMRNetwork3()
m_dmr3NetRewrites.push_back(rewrite);
}
std::vector<CTGDynRewriteStruct> dynRewrites = m_conf.getDMRNetwork3TGDynRewrites();
for (std::vector<CTGDynRewriteStruct>::const_iterator it = dynRewrites.begin(); it != dynRewrites.end(); ++it) {
LogInfo(" Dyn Rewrite: %u:TG%u-%u:TG%u <-> %u:TG%u (disc %u:TG%u)", (*it).m_slot, (*it).m_fromTG, (*it).m_slot, (*it).m_fromTG + (*it).m_range - 1U, (*it).m_slot, (*it).m_toTG, (*it).m_slot, (*it).m_discTG);
CRewriteDynTGNet* netRewriteDynTG = new CRewriteDynTGNet(m_dmr3Name, (*it).m_slot, (*it).m_fromTG, (*it).m_toTG, (*it).m_discTG, (*it).m_range);
CRewriteDynTGRF* rfRewriteDynTG = new CRewriteDynTGRF(m_dmr3Name, (*it).m_slot, (*it).m_fromTG, (*it).m_toTG, (*it).m_discTG, (*it).m_range, netRewriteDynTG);
m_dmr3RFRewrites.push_back(rfRewriteDynTG);
m_dmr3NetRewrites.push_back(netRewriteDynTG);
}
std::vector<CIdRewriteStruct> idRewrites = m_conf.getDMRNetwork3IdRewrites();
for (std::vector<CIdRewriteStruct>::const_iterator it = idRewrites.begin(); it != idRewrites.end(); ++it) {
LogInfo(" Rewrite Id: %u <-> %u", (*it).m_rfId, (*it).m_netId);
@@ -1747,6 +1782,17 @@ bool CDMRGateway::createDMRNetwork4()
m_dmr4NetRewrites.push_back(rewrite);
}
std::vector<CTGDynRewriteStruct> dynRewrites = m_conf.getDMRNetwork4TGDynRewrites();
for (std::vector<CTGDynRewriteStruct>::const_iterator it = dynRewrites.begin(); it != dynRewrites.end(); ++it) {
LogInfo(" Dyn Rewrite: %u:TG%u-%u:TG%u <-> %u:TG%u (disc %u:TG%u)", (*it).m_slot, (*it).m_fromTG, (*it).m_slot, (*it).m_fromTG + (*it).m_range - 1U, (*it).m_slot, (*it).m_toTG, (*it).m_slot, (*it).m_discTG);
CRewriteDynTGNet* netRewriteDynTG = new CRewriteDynTGNet(m_dmr4Name, (*it).m_slot, (*it).m_fromTG, (*it).m_toTG, (*it).m_discTG, (*it).m_range);
CRewriteDynTGRF* rfRewriteDynTG = new CRewriteDynTGRF(m_dmr4Name, (*it).m_slot, (*it).m_fromTG, (*it).m_toTG, (*it).m_discTG, (*it).m_range, netRewriteDynTG);
m_dmr4RFRewrites.push_back(rfRewriteDynTG);
m_dmr4NetRewrites.push_back(netRewriteDynTG);
}
std::vector<CIdRewriteStruct> idRewrites = m_conf.getDMRNetwork4IdRewrites();
for (std::vector<CIdRewriteStruct>::const_iterator it = idRewrites.begin(); it != idRewrites.end(); ++it) {
LogInfo(" Rewrite Id: %u <-> %u", (*it).m_rfId, (*it).m_netId);
@@ -1885,6 +1931,17 @@ bool CDMRGateway::createDMRNetwork5()
m_dmr5NetRewrites.push_back(rewrite);
}
std::vector<CTGDynRewriteStruct> dynRewrites = m_conf.getDMRNetwork5TGDynRewrites();
for (std::vector<CTGDynRewriteStruct>::const_iterator it = dynRewrites.begin(); it != dynRewrites.end(); ++it) {
LogInfo(" Dyn Rewrite: %u:TG%u-%u:TG%u <-> %u:TG%u (disc %u:TG%u)", (*it).m_slot, (*it).m_fromTG, (*it).m_slot, (*it).m_fromTG + (*it).m_range - 1U, (*it).m_slot, (*it).m_toTG, (*it).m_slot, (*it).m_discTG);
CRewriteDynTGNet* netRewriteDynTG = new CRewriteDynTGNet(m_dmr5Name, (*it).m_slot, (*it).m_fromTG, (*it).m_toTG, (*it).m_discTG, (*it).m_range);
CRewriteDynTGRF* rfRewriteDynTG = new CRewriteDynTGRF(m_dmr5Name, (*it).m_slot, (*it).m_fromTG, (*it).m_toTG, (*it).m_discTG, (*it).m_range, netRewriteDynTG);
m_dmr5RFRewrites.push_back(rfRewriteDynTG);
m_dmr5NetRewrites.push_back(netRewriteDynTG);
}
std::vector<CIdRewriteStruct> idRewrites = m_conf.getDMRNetwork5IdRewrites();
for (std::vector<CIdRewriteStruct>::const_iterator it = idRewrites.begin(); it != idRewrites.end(); ++it) {
LogInfo(" Rewrite Id: %u <-> %u", (*it).m_rfId, (*it).m_netId);

2
DMRGateway.ini
View File

@@ -70,6 +70,8 @@ TypeRewrite=1,9990,1,9990
SrcRewrite=1,9990,1,9990,1
# Reflector status returns
SrcRewrite=2,4000,2,9,1001
# Dynamic rewriting of slot 2 TGs 23500-23599 to TG9 to emulate reflector behaviour
TGDynRewrite=2,23500,4000,9,100
# Pass all of the other private traffic on slot 1 and slot 2
PassAllPC=1
PassAllPC=2

4
DMRGateway.vcxproj
View File

@@ -177,6 +177,8 @@
<ClInclude Include="RepeaterProtocol.h" />
<ClInclude Include="Rewrite.h" />
<ClInclude Include="RewriteDstId.h" />
<ClInclude Include="RewriteDynTGNet.h" />
<ClInclude Include="RewriteDynTGRF.h" />
<ClInclude Include="RewritePC.h" />
<ClInclude Include="RewriteSrc.h" />
<ClInclude Include="RewriteSrcId.h" />
@@ -219,6 +221,8 @@
<ClCompile Include="RepeaterProtocol.cpp" />
<ClCompile Include="Rewrite.cpp" />
<ClCompile Include="RewriteDstId.cpp" />
<ClCompile Include="RewriteDynTGNet.cpp" />
<ClCompile Include="RewriteDynTGRF.cpp" />
<ClCompile Include="RewritePC.cpp" />
<ClCompile Include="RewriteSrc.cpp" />
<ClCompile Include="RewriteSrcId.cpp" />

12
DMRGateway.vcxproj.filters
View File

@@ -134,6 +134,12 @@
<ClInclude Include="Reflectors.h">
<Filter>Header Files</Filter>
</ClInclude>
<ClInclude Include="RewriteDynTGNet.h">
<Filter>Header Files</Filter>
</ClInclude>
<ClInclude Include="RewriteDynTGRF.h">
<Filter>Header Files</Filter>
</ClInclude>
</ItemGroup>
<ItemGroup>
<ClCompile Include="Conf.cpp">
@@ -250,5 +256,11 @@
<ClCompile Include="Reflectors.cpp">
<Filter>Source Files</Filter>
</ClCompile>
<ClCompile Include="RewriteDynTGNet.cpp">
<Filter>Source Files</Filter>
</ClCompile>
<ClCompile Include="RewriteDynTGRF.cpp">
<Filter>Source Files</Filter>
</ClCompile>
</ItemGroup>
</Project>

5
Makefile
View File

@@ -5,8 +5,9 @@ LIBS = -lpthread
LDFLAGS = -g
OBJECTS = BPTC19696.o Conf.o CRC.o DMRCSBK.o DMRData.o DMRDataHeader.o DMREmbeddedData.o DMREMB.o DMRFullLC.o DMRGateway.o DMRLC.o DMRNetwork.o DMRSlotType.o \
Golay2087.o Hamming.o Log.o MMDVMNetwork.o PassAllPC.o PassAllTG.o QR1676.o Reflectors.o RepeaterProtocol.o Rewrite.o RewriteDstId.o RewritePC.o RewriteSrc.o \
RewriteSrcId.o RewriteTG.o RewriteType.o RS129.o SHA256.o StopWatch.o Sync.o Thread.o Timer.o UDPSocket.o Utils.o Voice.o
Golay2087.o Hamming.o Log.o MMDVMNetwork.o PassAllPC.o PassAllTG.o QR1676.o Reflectors.o RepeaterProtocol.o Rewrite.o RewriteDstId.o RewriteDynTGNet.o \
RewriteDynTGRF.o RewritePC.o RewriteSrc.o RewriteSrcId.o RewriteTG.o RewriteType.o RS129.o SHA256.o StopWatch.o Sync.o Thread.o Timer.o UDPSocket.o \
Utils.o Voice.o
all: DMRGateway

84
RewriteDynTGNet.cpp Normal file
View File

@@ -0,0 +1,84 @@
/*
* Copyright (C) 2017,2020 by Jonathan Naylor G4KLX
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#include "RewriteDynTGNet.h"
#include "DMRDefines.h"
#include "Log.h"
#include <cstdio>
#include <cassert>
CRewriteDynTGNet::CRewriteDynTGNet(const std::string& name, unsigned int slot, unsigned int fromTG, unsigned int toTG, unsigned int discTG, unsigned int range) :
CRewrite(),
m_name(name),
m_slot(slot),
m_fromTGStart(fromTG),
m_fromTGEnd(fromTG + range - 1U),
m_toTG(toTG),
m_discTG(discTG),
m_currentTG(0U)
{
assert(slot == 1U || slot == 2U);
}
CRewriteDynTGNet::~CRewriteDynTGNet()
{
}
bool CRewriteDynTGNet::process(CDMRData& data, bool trace)
{
FLCO flco = data.getFLCO();
unsigned int dstId = data.getDstId();
unsigned int slotNo = data.getSlotNo();
if (flco != FLCO_GROUP || slotNo != m_fromSlot || dstId < m_fromTGStart || dstId > m_fromTGEnd) {
if (trace) {
if (m_fromTGStart == m_fromTGEnd)
LogDebug("Rule Trace,\tRewriteDynTGNet from %s Slot=%u Dst=TG%u: not matched", m_name.c_str(), m_fromSlot, m_fromTGStart);
else
LogDebug("Rule Trace,\tRewriteDynTGNet from %s Slot=%u Dst=TG%u-TG%u: not matched", m_name.c_str(), m_fromSlot, m_fromTGStart, m_fromTGEnd);
}
return false;
}
if (m_fromSlot != m_toSlot)
data.setSlotNo(m_toSlot);
if (m_fromTGStart != m_toTGStart) {
unsigned int newTG = dstId + m_toTGStart - m_fromTGStart;
data.setDstId(newTG);
processMessage(data);
}
if (trace) {
if (m_fromTGStart == m_fromTGEnd)
LogDebug("Rule Trace,\tRewriteDynTGNet from %s Slot=%u Dst=TG%u: matched", m_name.c_str(), m_fromSlot, m_fromTGStart);
else
LogDebug("Rule Trace,\tRewriteDynTGNet from %s Slot=%u Dst=TG%u-TG%u: matched", m_name.c_str(), m_fromSlot, m_fromTGStart, m_fromTGEnd);
if (m_toTGStart == m_toTGEnd)
LogDebug("Rule Trace,\tRewriteDynTGNet to %s Slot=%u Dst=TG%u", m_name.c_str(), m_toSlot, m_toTGStart);
else
LogDebug("Rule Trace,\tRewriteDynTGNet to %s Slot=%u Dst=TG%u-TG%u", m_name.c_str(), m_toSlot, m_toTGStart, m_toTGEnd);
}
return true;
}

46
RewriteDynTGNet.h Normal file
View File

@@ -0,0 +1,46 @@
/*
* Copyright (C) 2017,2020 by Jonathan Naylor G4KLX
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#if !defined(REWRITEDYNTGNET_H)
#define REWRITEDYNTGNET_H
#include "Rewrite.h"
#include "DMRData.h"
#include <string>
class CRewriteDynTGNet : public CRewrite {
public:
CRewriteDynTGNet(const std::string& name, unsigned int slot, unsigned int fromTG, unsigned int toTG, unsigned int discTG, unsigned int range);
virtual ~CRewriteDynTGNet();
virtual bool process(CDMRData& data, bool trace);
void setCurrentTG(unsigned int tg);
private:
std::string m_name;
unsigned int m_slot;
unsigned int m_fromTGStart;
unsigned int m_fromTGEnd;
unsigned int m_toTG;
unsigned int m_discTG;
unsigned int m_currentTG;
};
#endif

86
RewriteDynTGRF.cpp Normal file
View File

@@ -0,0 +1,86 @@
/*
* Copyright (C) 2017,2020 by Jonathan Naylor G4KLX
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#include "RewriteDynTGRF.h"
#include "DMRDefines.h"
#include "Log.h"
#include <cstdio>
#include <cassert>
CRewriteDynTGRF::CRewriteDynTGRF(const std::string& name, unsigned int slot, unsigned int fromTG, unsigned int toTG, unsigned int discTG, unsigned int range, CRewriteDynTGNet* rewriteNet) :
CRewrite(),
m_name(name),
m_slot(slot),
m_fromTGStart(fromTG),
m_fromTGEnd(fromTG + range - 1U),
m_toTG(toTG),
m_discTG(discTG),
m_rewriteNet(rewriteNet),
m_currentTG(0U)
{
assert(slot == 1U || slot == 2U);
assert(rewriteNet != NULL);
}
CRewriteDynTGRF::~CRewriteDynTGRF()
{
}
bool CRewriteDynTGRF::process(CDMRData& data, bool trace)
{
FLCO flco = data.getFLCO();
unsigned int dstId = data.getDstId();
unsigned int slotNo = data.getSlotNo();
if (flco != FLCO_GROUP || slotNo != m_fromSlot || dstId < m_fromTGStart || dstId > m_fromTGEnd) {
if (trace) {
if (m_fromTGStart == m_fromTGEnd)
LogDebug("Rule Trace,\tRewriteDynTGRF from %s Slot=%u Dst=TG%u: not matched", m_name.c_str(), m_fromSlot, m_fromTGStart);
else
LogDebug("Rule Trace,\tRewriteDynTGRF from %s Slot=%u Dst=TG%u-TG%u: not matched", m_name.c_str(), m_fromSlot, m_fromTGStart, m_fromTGEnd);
}
return false;
}
if (m_fromSlot != m_toSlot)
data.setSlotNo(m_toSlot);
if (m_fromTGStart != m_toTGStart) {
unsigned int newTG = dstId + m_toTGStart - m_fromTGStart;
data.setDstId(newTG);
processMessage(data);
}
if (trace) {
if (m_fromTGStart == m_fromTGEnd)
LogDebug("Rule Trace,\tRewriteDynTGRF from %s Slot=%u Dst=TG%u: matched", m_name.c_str(), m_fromSlot, m_fromTGStart);
else
LogDebug("Rule Trace,\tRewriteDynTGRF from %s Slot=%u Dst=TG%u-TG%u: matched", m_name.c_str(), m_fromSlot, m_fromTGStart, m_fromTGEnd);
if (m_toTGStart == m_toTGEnd)
LogDebug("Rule Trace,\tRewriteDynTGRF to %s Slot=%u Dst=TG%u", m_name.c_str(), m_toSlot, m_toTGStart);
else
LogDebug("Rule Trace,\tRewriteDynTGRF to %s Slot=%u Dst=TG%u-TG%u", m_name.c_str(), m_toSlot, m_toTGStart, m_toTGEnd);
}
return true;
}

48
RewriteDynTGRF.h Normal file
View File

@@ -0,0 +1,48 @@
/*
* Copyright (C) 2017,2020 by Jonathan Naylor G4KLX
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#if !defined(REWRITEDYNTGRF_H)
#define REWRITEDYNTGRF_H
#include "Rewrite.h"
#include "DMRData.h"
#include "RewriteDynTGNet.h"
#include <string>
class CRewriteDynTGRF : public CRewrite {
public:
CRewriteDynTGRF(const std::string& name, unsigned int slot, unsigned int fromTG, unsigned int toTG, unsigned int discTG, unsigned int range, CRewriteDynTGNet* rewriteNet);
virtual ~CRewriteDynTGRF();
virtual bool process(CDMRData& data, bool trace);
private:
std::string m_name;
unsigned int m_slot;
unsigned int m_fromTGStart;
unsigned int m_fromTGEnd;
unsigned int m_toTG;
unsigned int m_discTG;
CRewriteDynTGNet* m_rewriteNet;
unsigned int m_currentTG;
};
#endif