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Add basic rule tracing.

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This commit is contained in:
Jonathan Naylor
2017-06-04 15:17:43 +01:00
parent efbf42ff83
commit 2e257da997
17 changed files with 177 additions and 56 deletions
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8
Conf.cpp
View File

@@ -45,6 +45,7 @@ m_rptPort(62032U),
m_localAddress("127.0.0.1"), m_localAddress("127.0.0.1"),
m_localPort(62031U), m_localPort(62031U),
m_timeout(10U), m_timeout(10U),
m_ruleTrace(false),
m_debug(false), m_debug(false),
m_voiceEnabled(true), m_voiceEnabled(true),
m_voiceLanguage("en_GB"), m_voiceLanguage("en_GB"),
@@ -169,6 +170,8 @@ bool CConf::read()
m_localAddress = value; m_localAddress = value;
else if (::strcmp(key, "LocalPort") == 0) else if (::strcmp(key, "LocalPort") == 0)
m_localPort = (unsigned int)::atoi(value); m_localPort = (unsigned int)::atoi(value);
else if (::strcmp(key, "RuleTrace") == 0)
m_ruleTrace = ::atoi(value) == 1;
else if (::strcmp(key, "Debug") == 0) else if (::strcmp(key, "Debug") == 0)
m_debug = ::atoi(value) == 1; m_debug = ::atoi(value) == 1;
} else if (section == SECTION_LOG) { } else if (section == SECTION_LOG) {
@@ -439,6 +442,11 @@ unsigned int CConf::getTimeout() const
return m_timeout; return m_timeout;
} }
bool CConf::getRuleTrace() const
{
return m_ruleTrace;
}
bool CConf::getDebug() const bool CConf::getDebug() const
{ {
return m_debug; return m_debug;

2
Conf.h
View File

@@ -68,6 +68,7 @@ public:
unsigned int getRptPort() const; unsigned int getRptPort() const;
std::string getLocalAddress() const; std::string getLocalAddress() const;
unsigned int getLocalPort() const; unsigned int getLocalPort() const;
bool getRuleTrace() const;
bool getDebug() const; bool getDebug() const;
// The Log section // The Log section
@@ -149,6 +150,7 @@ private:
std::string m_localAddress; std::string m_localAddress;
unsigned int m_localPort; unsigned int m_localPort;
unsigned int m_timeout; unsigned int m_timeout;
bool m_ruleTrace;
bool m_debug; bool m_debug;
bool m_voiceEnabled; bool m_voiceEnabled;

85
DMRGateway.cpp
View File

@@ -127,6 +127,7 @@ int main(int argc, char** argv)
CDMRGateway::CDMRGateway(const std::string& confFile) : CDMRGateway::CDMRGateway(const std::string& confFile) :
m_conf(confFile), m_conf(confFile),
m_ruleTrace(false),
m_repeater(NULL), m_repeater(NULL),
m_dmrNetwork1(NULL), m_dmrNetwork1(NULL),
m_dmrNetwork2(NULL), m_dmrNetwork2(NULL),
@@ -342,6 +343,9 @@ int CDMRGateway::run()
} }
} }
m_ruleTrace = m_conf.getRuleTrace();
LogInfo("Rule trace: %s", m_ruleTrace ? "yes" : "no");
CTimer* timer[3U]; CTimer* timer[3U];
timer[1U] = new CTimer(1000U, timeout); timer[1U] = new CTimer(1000U, timeout);
timer[2U] = new CTimer(1000U, timeout); timer[2U] = new CTimer(1000U, timeout);
@@ -508,6 +512,14 @@ int CDMRGateway::run()
} }
} }
} else { } else {
unsigned int slotNo = data.getSlotNo();
unsigned int srcId = data.getSrcId();
unsigned int dstId = data.getDstId();
FLCO flco = data.getFLCO();
if (m_ruleTrace)
LogDebug("Rule Trace, RF transmission: S%u %u -> %s%u", slotNo, srcId, flco == FLCO_GROUP ? "TG" : "", dstId);
bool rewritten = false; bool rewritten = false;
if (m_dmrNetwork1 != NULL) { if (m_dmrNetwork1 != NULL) {
@@ -521,7 +533,6 @@ int CDMRGateway::run()
} }
if (rewritten) { if (rewritten) {
unsigned int slotNo = data.getSlotNo();
if (status[slotNo] == DMRGWS_NONE || status[slotNo] == DMRGWS_DMRNETWORK1) { if (status[slotNo] == DMRGWS_NONE || status[slotNo] == DMRGWS_DMRNETWORK1) {
m_dmrNetwork1->write(data); m_dmrNetwork1->write(data);
status[slotNo] = DMRGWS_DMRNETWORK1; status[slotNo] = DMRGWS_DMRNETWORK1;
@@ -542,7 +553,6 @@ int CDMRGateway::run()
} }
if (rewritten) { if (rewritten) {
unsigned int slotNo = data.getSlotNo();
if (status[slotNo] == DMRGWS_NONE || status[slotNo] == DMRGWS_DMRNETWORK2) { if (status[slotNo] == DMRGWS_NONE || status[slotNo] == DMRGWS_DMRNETWORK2) {
m_dmrNetwork2->write(data); m_dmrNetwork2->write(data);
status[slotNo] = DMRGWS_DMRNETWORK2; status[slotNo] = DMRGWS_DMRNETWORK2;
@@ -551,6 +561,9 @@ int CDMRGateway::run()
} }
} }
} }
if (!rewritten && m_ruleTrace)
LogDebug("Rule Trace,\tnot matched so rejected");
} }
} }
@@ -596,6 +609,14 @@ int CDMRGateway::run()
if (m_dmrNetwork1 != NULL) { if (m_dmrNetwork1 != NULL) {
ret = m_dmrNetwork1->read(data); ret = m_dmrNetwork1->read(data);
if (ret) { if (ret) {
unsigned int slotNo = data.getSlotNo();
unsigned int srcId = data.getSrcId();
unsigned int dstId = data.getDstId();
FLCO flco = data.getFLCO();
if (m_ruleTrace)
LogDebug("Rule Trace, network 1 transmission: S%u %u -> %s%u", slotNo, srcId, flco == FLCO_GROUP ? "TG" : "", dstId);
// Rewrite the slot and/or TG or neither // Rewrite the slot and/or TG or neither
bool rewritten = false; bool rewritten = false;
for (std::vector<IRewrite*>::iterator it = m_dmr1NetRewrites.begin(); it != m_dmr1NetRewrites.end(); ++it) { for (std::vector<IRewrite*>::iterator it = m_dmr1NetRewrites.begin(); it != m_dmr1NetRewrites.end(); ++it) {
@@ -607,13 +628,15 @@ int CDMRGateway::run()
} }
if (rewritten) { if (rewritten) {
unsigned int slotNo = data.getSlotNo();
if (status[slotNo] == DMRGWS_NONE || status[slotNo] == DMRGWS_DMRNETWORK1) { if (status[slotNo] == DMRGWS_NONE || status[slotNo] == DMRGWS_DMRNETWORK1) {
m_repeater->write(data); m_repeater->write(data);
status[slotNo] = DMRGWS_DMRNETWORK1; status[slotNo] = DMRGWS_DMRNETWORK1;
timer[slotNo]->start(); timer[slotNo]->start();
} }
} }
if (!rewritten && m_ruleTrace)
LogDebug("Rule Trace,\tnot matched so rejected");
} }
ret = m_dmrNetwork1->wantsBeacon(); ret = m_dmrNetwork1->wantsBeacon();
@@ -624,6 +647,14 @@ int CDMRGateway::run()
if (m_dmrNetwork2 != NULL) { if (m_dmrNetwork2 != NULL) {
ret = m_dmrNetwork2->read(data); ret = m_dmrNetwork2->read(data);
if (ret) { if (ret) {
unsigned int slotNo = data.getSlotNo();
unsigned int srcId = data.getSrcId();
unsigned int dstId = data.getDstId();
FLCO flco = data.getFLCO();
if (m_ruleTrace)
LogDebug("Rule Trace, network 2 transmission: S%u %u -> %s%u", slotNo, srcId, flco == FLCO_GROUP ? "TG" : "", dstId);
// Rewrite the slot and/or TG or neither // Rewrite the slot and/or TG or neither
bool rewritten = false; bool rewritten = false;
for (std::vector<IRewrite*>::iterator it = m_dmr2NetRewrites.begin(); it != m_dmr2NetRewrites.end(); ++it) { for (std::vector<IRewrite*>::iterator it = m_dmr2NetRewrites.begin(); it != m_dmr2NetRewrites.end(); ++it) {
@@ -635,13 +666,15 @@ int CDMRGateway::run()
} }
if (rewritten) { if (rewritten) {
unsigned int slotNo = data.getSlotNo();
if (status[slotNo] == DMRGWS_NONE || status[slotNo] == DMRGWS_DMRNETWORK2) { if (status[slotNo] == DMRGWS_NONE || status[slotNo] == DMRGWS_DMRNETWORK2) {
m_repeater->write(data); m_repeater->write(data);
status[slotNo] = DMRGWS_DMRNETWORK2; status[slotNo] = DMRGWS_DMRNETWORK2;
timer[slotNo]->start(); timer[slotNo]->start();
} }
} }
if (!rewritten && m_ruleTrace)
LogDebug("Rule Trace,\tnot matched so rejected");
} }
ret = m_dmrNetwork2->wantsBeacon(); ret = m_dmrNetwork2->wantsBeacon();
@@ -836,8 +869,8 @@ bool CDMRGateway::createDMRNetwork1()
LogInfo(" Rewrite RF: %u:TG%u-TG%u -> %u:TG%u-TG%u", (*it).m_fromSlot, (*it).m_fromTG, (*it).m_fromTG + (*it).m_range - 1U, (*it).m_toSlot, (*it).m_toTG, (*it).m_toTG + (*it).m_range - 1U); LogInfo(" Rewrite RF: %u:TG%u-TG%u -> %u:TG%u-TG%u", (*it).m_fromSlot, (*it).m_fromTG, (*it).m_fromTG + (*it).m_range - 1U, (*it).m_toSlot, (*it).m_toTG, (*it).m_toTG + (*it).m_range - 1U);
LogInfo(" Rewrite Net: %u:TG%u-TG%u -> %u:TG%u-TG%u", (*it).m_toSlot, (*it).m_toTG, (*it).m_toTG + (*it).m_range - 1U, (*it).m_fromSlot, (*it).m_fromTG, (*it).m_fromTG + (*it).m_range - 1U); LogInfo(" Rewrite Net: %u:TG%u-TG%u -> %u:TG%u-TG%u", (*it).m_toSlot, (*it).m_toTG, (*it).m_toTG + (*it).m_range - 1U, (*it).m_fromSlot, (*it).m_fromTG, (*it).m_fromTG + (*it).m_range - 1U);
CRewriteTG* rfRewrite = new CRewriteTG("DMR-1", (*it).m_fromSlot, (*it).m_fromTG, (*it).m_toSlot, (*it).m_toTG, (*it).m_range); CRewriteTG* rfRewrite = new CRewriteTG("DMR-1", (*it).m_fromSlot, (*it).m_fromTG, (*it).m_toSlot, (*it).m_toTG, (*it).m_range, m_ruleTrace);
CRewriteTG* netRewrite = new CRewriteTG("DMR-1", (*it).m_toSlot, (*it).m_toTG, (*it).m_fromSlot, (*it).m_fromTG, (*it).m_range); CRewriteTG* netRewrite = new CRewriteTG("DMR-1", (*it).m_toSlot, (*it).m_toTG, (*it).m_fromSlot, (*it).m_fromTG, (*it).m_range, m_ruleTrace);
m_dmr1RFRewrites.push_back(rfRewrite); m_dmr1RFRewrites.push_back(rfRewrite);
m_dmr1NetRewrites.push_back(netRewrite); m_dmr1NetRewrites.push_back(netRewrite);
@@ -847,7 +880,7 @@ bool CDMRGateway::createDMRNetwork1()
for (std::vector<CPCRewriteStruct>::const_iterator it = pcRewrites.begin(); it != pcRewrites.end(); ++it) { for (std::vector<CPCRewriteStruct>::const_iterator it = pcRewrites.begin(); it != pcRewrites.end(); ++it) {
LogInfo(" Rewrite RF: %u:%u-%u -> %u:%u-%u", (*it).m_fromSlot, (*it).m_fromId, (*it).m_fromId + (*it).m_range - 1U, (*it).m_toSlot, (*it).m_toId, (*it).m_toId + (*it).m_range - 1U); LogInfo(" Rewrite RF: %u:%u-%u -> %u:%u-%u", (*it).m_fromSlot, (*it).m_fromId, (*it).m_fromId + (*it).m_range - 1U, (*it).m_toSlot, (*it).m_toId, (*it).m_toId + (*it).m_range - 1U);
CRewritePC* rewrite = new CRewritePC("DMR-1", (*it).m_fromSlot, (*it).m_fromId, (*it).m_toSlot, (*it).m_toId, (*it).m_range); CRewritePC* rewrite = new CRewritePC("DMR-1", (*it).m_fromSlot, (*it).m_fromId, (*it).m_toSlot, (*it).m_toId, (*it).m_range, m_ruleTrace);
m_dmr1RFRewrites.push_back(rewrite); m_dmr1RFRewrites.push_back(rewrite);
} }
@@ -856,7 +889,7 @@ bool CDMRGateway::createDMRNetwork1()
for (std::vector<CTypeRewriteStruct>::const_iterator it = typeRewrites.begin(); it != typeRewrites.end(); ++it) { for (std::vector<CTypeRewriteStruct>::const_iterator it = typeRewrites.begin(); it != typeRewrites.end(); ++it) {
LogInfo(" Rewrite RF: %u:TG%u -> %u:%u", (*it).m_fromSlot, (*it).m_fromTG, (*it).m_toSlot, (*it).m_toId); LogInfo(" Rewrite RF: %u:TG%u -> %u:%u", (*it).m_fromSlot, (*it).m_fromTG, (*it).m_toSlot, (*it).m_toId);
CRewriteType* rewrite = new CRewriteType("DMR-1", (*it).m_fromSlot, (*it).m_fromTG, (*it).m_toSlot, (*it).m_toId); CRewriteType* rewrite = new CRewriteType("DMR-1", (*it).m_fromSlot, (*it).m_fromTG, (*it).m_toSlot, (*it).m_toId, m_ruleTrace);
m_dmr1RFRewrites.push_back(rewrite); m_dmr1RFRewrites.push_back(rewrite);
} }
@@ -865,7 +898,7 @@ bool CDMRGateway::createDMRNetwork1()
for (std::vector<CSrcRewriteStruct>::const_iterator it = srcRewrites.begin(); it != srcRewrites.end(); ++it) { for (std::vector<CSrcRewriteStruct>::const_iterator it = srcRewrites.begin(); it != srcRewrites.end(); ++it) {
LogInfo(" Rewrite Net: %u:%u-%u -> %u:TG%u", (*it).m_fromSlot, (*it).m_fromId, (*it).m_fromId + (*it).m_range - 1U, (*it).m_toSlot, (*it).m_toTG); LogInfo(" Rewrite Net: %u:%u-%u -> %u:TG%u", (*it).m_fromSlot, (*it).m_fromId, (*it).m_fromId + (*it).m_range - 1U, (*it).m_toSlot, (*it).m_toTG);
CRewriteSrc* rewrite = new CRewriteSrc("DMR-1", (*it).m_fromSlot, (*it).m_fromId, (*it).m_toSlot, (*it).m_toTG, (*it).m_range); CRewriteSrc* rewrite = new CRewriteSrc("DMR-1", (*it).m_fromSlot, (*it).m_fromId, (*it).m_toSlot, (*it).m_toTG, (*it).m_range, m_ruleTrace);
m_dmr1NetRewrites.push_back(rewrite); m_dmr1NetRewrites.push_back(rewrite);
} }
@@ -874,8 +907,8 @@ bool CDMRGateway::createDMRNetwork1()
for (std::vector<unsigned int>::const_iterator it = tgPassAll.begin(); it != tgPassAll.end(); ++it) { for (std::vector<unsigned int>::const_iterator it = tgPassAll.begin(); it != tgPassAll.end(); ++it) {
LogInfo(" Pass All TG: %u", *it); LogInfo(" Pass All TG: %u", *it);
CPassAllTG* rfPassAllTG = new CPassAllTG("DMR-1", *it); CPassAllTG* rfPassAllTG = new CPassAllTG("DMR-1", *it, m_ruleTrace);
CPassAllTG* netPassAllTG = new CPassAllTG("DMR-1", *it); CPassAllTG* netPassAllTG = new CPassAllTG("DMR-1", *it, m_ruleTrace);
m_dmr1RFRewrites.push_back(rfPassAllTG); m_dmr1RFRewrites.push_back(rfPassAllTG);
m_dmr1NetRewrites.push_back(netPassAllTG); m_dmr1NetRewrites.push_back(netPassAllTG);
@@ -885,8 +918,8 @@ bool CDMRGateway::createDMRNetwork1()
for (std::vector<unsigned int>::const_iterator it = pcPassAll.begin(); it != pcPassAll.end(); ++it) { for (std::vector<unsigned int>::const_iterator it = pcPassAll.begin(); it != pcPassAll.end(); ++it) {
LogInfo(" Pass All PC: %u", *it); LogInfo(" Pass All PC: %u", *it);
CPassAllPC* rfPassAllPC = new CPassAllPC("DMR-1", *it); CPassAllPC* rfPassAllPC = new CPassAllPC("DMR-1", *it, m_ruleTrace);
CPassAllPC* netPassAllPC = new CPassAllPC("DMR-1", *it); CPassAllPC* netPassAllPC = new CPassAllPC("DMR-1", *it, m_ruleTrace);
m_dmr1RFRewrites.push_back(rfPassAllPC); m_dmr1RFRewrites.push_back(rfPassAllPC);
m_dmr1NetRewrites.push_back(netPassAllPC); m_dmr1NetRewrites.push_back(netPassAllPC);
@@ -944,8 +977,8 @@ bool CDMRGateway::createDMRNetwork2()
LogInfo(" Rewrite RF: %u:TG%u-TG%u -> %u:TG%u-TG%u", (*it).m_fromSlot, (*it).m_fromTG, (*it).m_fromTG + (*it).m_range - 1U, (*it).m_toSlot, (*it).m_toTG, (*it).m_toTG + (*it).m_range - 1U); LogInfo(" Rewrite RF: %u:TG%u-TG%u -> %u:TG%u-TG%u", (*it).m_fromSlot, (*it).m_fromTG, (*it).m_fromTG + (*it).m_range - 1U, (*it).m_toSlot, (*it).m_toTG, (*it).m_toTG + (*it).m_range - 1U);
LogInfo(" Rewrite Net: %u:TG%u-TG%u -> %u:TG%u-TG%u", (*it).m_toSlot, (*it).m_toTG, (*it).m_toTG + (*it).m_range - 1U, (*it).m_fromSlot, (*it).m_fromTG, (*it).m_fromTG + (*it).m_range - 1U); LogInfo(" Rewrite Net: %u:TG%u-TG%u -> %u:TG%u-TG%u", (*it).m_toSlot, (*it).m_toTG, (*it).m_toTG + (*it).m_range - 1U, (*it).m_fromSlot, (*it).m_fromTG, (*it).m_fromTG + (*it).m_range - 1U);
CRewriteTG* rfRewrite = new CRewriteTG("DMR-2", (*it).m_fromSlot, (*it).m_fromTG, (*it).m_toSlot, (*it).m_toTG, (*it).m_range); CRewriteTG* rfRewrite = new CRewriteTG("DMR-2", (*it).m_fromSlot, (*it).m_fromTG, (*it).m_toSlot, (*it).m_toTG, (*it).m_range, m_ruleTrace);
CRewriteTG* netRewrite = new CRewriteTG("DMR-2", (*it).m_toSlot, (*it).m_toTG, (*it).m_fromSlot, (*it).m_fromTG, (*it).m_range); CRewriteTG* netRewrite = new CRewriteTG("DMR-2", (*it).m_toSlot, (*it).m_toTG, (*it).m_fromSlot, (*it).m_fromTG, (*it).m_range, m_ruleTrace);
m_dmr2RFRewrites.push_back(rfRewrite); m_dmr2RFRewrites.push_back(rfRewrite);
m_dmr2NetRewrites.push_back(netRewrite); m_dmr2NetRewrites.push_back(netRewrite);
@@ -955,7 +988,7 @@ bool CDMRGateway::createDMRNetwork2()
for (std::vector<CPCRewriteStruct>::const_iterator it = pcRewrites.begin(); it != pcRewrites.end(); ++it) { for (std::vector<CPCRewriteStruct>::const_iterator it = pcRewrites.begin(); it != pcRewrites.end(); ++it) {
LogInfo(" Rewrite RF: %u:%u-%u -> %u:%u-%u", (*it).m_fromSlot, (*it).m_fromId, (*it).m_fromId + (*it).m_range - 1U, (*it).m_toSlot, (*it).m_toId, (*it).m_toId + (*it).m_range - 1U); LogInfo(" Rewrite RF: %u:%u-%u -> %u:%u-%u", (*it).m_fromSlot, (*it).m_fromId, (*it).m_fromId + (*it).m_range - 1U, (*it).m_toSlot, (*it).m_toId, (*it).m_toId + (*it).m_range - 1U);
CRewritePC* rewrite = new CRewritePC("DMR-2", (*it).m_fromSlot, (*it).m_fromId, (*it).m_toSlot, (*it).m_toId, (*it).m_range); CRewritePC* rewrite = new CRewritePC("DMR-2", (*it).m_fromSlot, (*it).m_fromId, (*it).m_toSlot, (*it).m_toId, (*it).m_range, m_ruleTrace);
m_dmr2RFRewrites.push_back(rewrite); m_dmr2RFRewrites.push_back(rewrite);
} }
@@ -964,7 +997,7 @@ bool CDMRGateway::createDMRNetwork2()
for (std::vector<CTypeRewriteStruct>::const_iterator it = typeRewrites.begin(); it != typeRewrites.end(); ++it) { for (std::vector<CTypeRewriteStruct>::const_iterator it = typeRewrites.begin(); it != typeRewrites.end(); ++it) {
LogInfo(" Rewrite RF: %u:TG%u -> %u:%u", (*it).m_fromSlot, (*it).m_fromTG, (*it).m_toSlot, (*it).m_toId); LogInfo(" Rewrite RF: %u:TG%u -> %u:%u", (*it).m_fromSlot, (*it).m_fromTG, (*it).m_toSlot, (*it).m_toId);
CRewriteType* rewrite = new CRewriteType("DMR-2", (*it).m_fromSlot, (*it).m_fromTG, (*it).m_toSlot, (*it).m_toId); CRewriteType* rewrite = new CRewriteType("DMR-2", (*it).m_fromSlot, (*it).m_fromTG, (*it).m_toSlot, (*it).m_toId, m_ruleTrace);
m_dmr2RFRewrites.push_back(rewrite); m_dmr2RFRewrites.push_back(rewrite);
} }
@@ -973,7 +1006,7 @@ bool CDMRGateway::createDMRNetwork2()
for (std::vector<CSrcRewriteStruct>::const_iterator it = srcRewrites.begin(); it != srcRewrites.end(); ++it) { for (std::vector<CSrcRewriteStruct>::const_iterator it = srcRewrites.begin(); it != srcRewrites.end(); ++it) {
LogInfo(" Rewrite Net: %u:%u-%u -> %u:TG%u", (*it).m_fromSlot, (*it).m_fromId, (*it).m_fromId + (*it).m_range - 1U, (*it).m_toSlot, (*it).m_toTG); LogInfo(" Rewrite Net: %u:%u-%u -> %u:TG%u", (*it).m_fromSlot, (*it).m_fromId, (*it).m_fromId + (*it).m_range - 1U, (*it).m_toSlot, (*it).m_toTG);
CRewriteSrc* rewrite = new CRewriteSrc("DMR-2", (*it).m_fromSlot, (*it).m_fromId, (*it).m_toSlot, (*it).m_toTG, (*it).m_range); CRewriteSrc* rewrite = new CRewriteSrc("DMR-2", (*it).m_fromSlot, (*it).m_fromId, (*it).m_toSlot, (*it).m_toTG, (*it).m_range, m_ruleTrace);
m_dmr2NetRewrites.push_back(rewrite); m_dmr2NetRewrites.push_back(rewrite);
} }
@@ -982,8 +1015,8 @@ bool CDMRGateway::createDMRNetwork2()
for (std::vector<unsigned int>::const_iterator it = tgPassAll.begin(); it != tgPassAll.end(); ++it) { for (std::vector<unsigned int>::const_iterator it = tgPassAll.begin(); it != tgPassAll.end(); ++it) {
LogInfo(" Pass All TG: %u", *it); LogInfo(" Pass All TG: %u", *it);
CPassAllTG* rfPassAllTG = new CPassAllTG("DMR-2", *it); CPassAllTG* rfPassAllTG = new CPassAllTG("DMR-2", *it, m_ruleTrace);
CPassAllTG* netPassAllTG = new CPassAllTG("DMR-2", *it); CPassAllTG* netPassAllTG = new CPassAllTG("DMR-2", *it, m_ruleTrace);
m_dmr2RFRewrites.push_back(rfPassAllTG); m_dmr2RFRewrites.push_back(rfPassAllTG);
m_dmr2NetRewrites.push_back(netPassAllTG); m_dmr2NetRewrites.push_back(netPassAllTG);
@@ -993,8 +1026,8 @@ bool CDMRGateway::createDMRNetwork2()
for (std::vector<unsigned int>::const_iterator it = pcPassAll.begin(); it != pcPassAll.end(); ++it) { for (std::vector<unsigned int>::const_iterator it = pcPassAll.begin(); it != pcPassAll.end(); ++it) {
LogInfo(" Pass All PC: %u", *it); LogInfo(" Pass All PC: %u", *it);
CPassAllPC* rfPassAllPC = new CPassAllPC("DMR-2", *it); CPassAllPC* rfPassAllPC = new CPassAllPC("DMR-2", *it, m_ruleTrace);
CPassAllPC* netPassAllPC = new CPassAllPC("DMR-2", *it); CPassAllPC* netPassAllPC = new CPassAllPC("DMR-2", *it, m_ruleTrace);
m_dmr2RFRewrites.push_back(rfPassAllPC); m_dmr2RFRewrites.push_back(rfPassAllPC);
m_dmr2NetRewrites.push_back(netPassAllPC); m_dmr2NetRewrites.push_back(netPassAllPC);
@@ -1055,8 +1088,8 @@ bool CDMRGateway::createXLXNetwork1()
if (m_xlx1Startup != 4000U) if (m_xlx1Startup != 4000U)
LogInfo(" Startup: %u", m_xlx1Startup); LogInfo(" Startup: %u", m_xlx1Startup);
m_rpt1Rewrite = new CRewriteTG("XLX-1", XLX_SLOT, XLX_TG, m_xlx1Slot, m_xlx1TG, 1U); m_rpt1Rewrite = new CRewriteTG("XLX-1", XLX_SLOT, XLX_TG, m_xlx1Slot, m_xlx1TG, 1U, false);
m_xlx1Rewrite = new CRewriteTG("XLX-1", m_xlx1Slot, m_xlx1TG, XLX_SLOT, XLX_TG, 1U); m_xlx1Rewrite = new CRewriteTG("XLX-1", m_xlx1Slot, m_xlx1TG, XLX_SLOT, XLX_TG, 1U, false);
return true; return true;
} }
@@ -1113,8 +1146,8 @@ bool CDMRGateway::createXLXNetwork2()
if (m_xlx2Startup != 4000U) if (m_xlx2Startup != 4000U)
LogInfo(" Startup: %u", m_xlx2Startup); LogInfo(" Startup: %u", m_xlx2Startup);
m_rpt2Rewrite = new CRewriteTG("XLX-2", XLX_SLOT, XLX_TG, m_xlx2Slot, m_xlx2TG, 1U); m_rpt2Rewrite = new CRewriteTG("XLX-2", XLX_SLOT, XLX_TG, m_xlx2Slot, m_xlx2TG, 1U, false);
m_xlx2Rewrite = new CRewriteTG("XLX-2", m_xlx2Slot, m_xlx2TG, XLX_SLOT, XLX_TG, 1U); m_xlx2Rewrite = new CRewriteTG("XLX-2", m_xlx2Slot, m_xlx2TG, XLX_SLOT, XLX_TG, 1U, false);
return true; return true;
} }

1
DMRGateway.h
View File

@@ -38,6 +38,7 @@ public:
private: private:
CConf m_conf; CConf m_conf;
bool m_ruleTrace;
IRepeaterProtocol* m_repeater; IRepeaterProtocol* m_repeater;
CDMRNetwork* m_dmrNetwork1; CDMRNetwork* m_dmrNetwork1;
CDMRNetwork* m_dmrNetwork2; CDMRNetwork* m_dmrNetwork2;

1
DMRGateway.ini
View File

@@ -4,6 +4,7 @@ RptAddress=127.0.0.1
RptPort=62032 RptPort=62032
LocalAddress=127.0.0.1 LocalAddress=127.0.0.1
LocalPort=62031 LocalPort=62031
RuleTrace=0
Daemon=0 Daemon=0
Debug=0 Debug=0

20
PassAllPC.cpp
View File

@@ -19,13 +19,15 @@
#include "PassAllPC.h" #include "PassAllPC.h"
#include "DMRDefines.h" #include "DMRDefines.h"
#include "Log.h"
#include <cstdio> #include <cstdio>
#include <cassert> #include <cassert>
CPassAllPC::CPassAllPC(const char* name, unsigned int slot) : CPassAllPC::CPassAllPC(const char* name, unsigned int slot, bool trace) :
m_name(name), m_name(name),
m_slot(slot) m_slot(slot),
m_trace(trace)
{ {
assert(slot == 1U || slot == 2U); assert(slot == 1U || slot == 2U);
} }
@@ -36,12 +38,22 @@ CPassAllPC::~CPassAllPC()
bool CPassAllPC::processRF(CDMRData& data) bool CPassAllPC::processRF(CDMRData& data)
{ {
return process(data); bool ret = process(data);
if (m_trace)
LogDebug("Rule Trace,\tPassAllPC %s Slot=%u: %s", m_name, m_slot, ret ? "matched" : "not matched");
return ret;
} }
bool CPassAllPC::processNet(CDMRData& data) bool CPassAllPC::processNet(CDMRData& data)
{ {
return process(data); bool ret = process(data);
if (m_trace)
LogDebug("Rule Trace,\tPassAllPC %s Slot=%u: %s", m_name, m_slot, ret ? "matched" : "not matched");
return ret;
} }
bool CPassAllPC::process(CDMRData& data) bool CPassAllPC::process(CDMRData& data)

3
PassAllPC.h
View File

@@ -24,7 +24,7 @@
class CPassAllPC : public IRewrite { class CPassAllPC : public IRewrite {
public: public:
CPassAllPC(const char* name, unsigned int slot); CPassAllPC(const char* name, unsigned int slot, bool trace);
virtual ~CPassAllPC(); virtual ~CPassAllPC();
virtual bool processRF(CDMRData& data); virtual bool processRF(CDMRData& data);
@@ -33,6 +33,7 @@ public:
private: private:
const char* m_name; const char* m_name;
unsigned int m_slot; unsigned int m_slot;
bool m_trace;
bool process(CDMRData& data); bool process(CDMRData& data);
}; };

20
PassAllTG.cpp
View File

@@ -19,13 +19,15 @@
#include "PassAllTG.h" #include "PassAllTG.h"
#include "DMRDefines.h" #include "DMRDefines.h"
#include "Log.h"
#include <cstdio> #include <cstdio>
#include <cassert> #include <cassert>
CPassAllTG::CPassAllTG(const char* name, unsigned int slot) : CPassAllTG::CPassAllTG(const char* name, unsigned int slot, bool trace) :
m_name(name), m_name(name),
m_slot(slot) m_slot(slot),
m_trace(trace)
{ {
assert(slot == 1U || slot == 2U); assert(slot == 1U || slot == 2U);
} }
@@ -36,12 +38,22 @@ CPassAllTG::~CPassAllTG()
bool CPassAllTG::processRF(CDMRData& data) bool CPassAllTG::processRF(CDMRData& data)
{ {
return process(data); bool ret = process(data);
if (m_trace)
LogDebug("Rule Trace,\tPassAllTG %s Slot=%u: %s", m_name, m_slot, ret ? "matched" : "not matched");
return ret;
} }
bool CPassAllTG::processNet(CDMRData& data) bool CPassAllTG::processNet(CDMRData& data)
{ {
return process(data); bool ret = process(data);
if (m_trace)
LogDebug("Rule Trace,\tPassAllTG %s Slot=%u: %s", m_name, m_slot, ret ? "matched" : "not matched");
return ret;
} }
bool CPassAllTG::process(CDMRData& data) bool CPassAllTG::process(CDMRData& data)

3
PassAllTG.h
View File

@@ -24,7 +24,7 @@
class CPassAllTG : public IRewrite { class CPassAllTG : public IRewrite {
public: public:
CPassAllTG(const char* name, unsigned int slot); CPassAllTG(const char* name, unsigned int slot, bool trace);
virtual ~CPassAllTG(); virtual ~CPassAllTG();
virtual bool processRF(CDMRData& data); virtual bool processRF(CDMRData& data);
@@ -33,6 +33,7 @@ public:
private: private:
const char* m_name; const char* m_name;
unsigned int m_slot; unsigned int m_slot;
bool m_trace;
bool process(CDMRData& data); bool process(CDMRData& data);
}; };

18
RewritePC.cpp
View File

@@ -20,17 +20,19 @@
#include "DMRDefines.h" #include "DMRDefines.h"
#include "DMRFullLC.h" #include "DMRFullLC.h"
#include "Log.h"
#include <cstdio> #include <cstdio>
#include <cassert> #include <cassert>
CRewritePC::CRewritePC(const char* name, unsigned int fromSlot, unsigned int fromId, unsigned int toSlot, unsigned int toId, unsigned int range) : CRewritePC::CRewritePC(const char* name, unsigned int fromSlot, unsigned int fromId, unsigned int toSlot, unsigned int toId, unsigned int range, bool trace) :
m_name(name), m_name(name),
m_fromSlot(fromSlot), m_fromSlot(fromSlot),
m_fromIdStart(fromId), m_fromIdStart(fromId),
m_fromIdEnd(fromId + range), m_fromIdEnd(fromId + range),
m_toSlot(toSlot), m_toSlot(toSlot),
m_toIdStart(toId), m_toIdStart(toId),
m_trace(trace),
m_lc(FLCO_USER_USER, 0U, 0U), m_lc(FLCO_USER_USER, 0U, 0U),
m_embeddedLC() m_embeddedLC()
{ {
@@ -44,12 +46,22 @@ CRewritePC::~CRewritePC()
bool CRewritePC::processRF(CDMRData& data) bool CRewritePC::processRF(CDMRData& data)
{ {
return process(data); bool ret = process(data);
if (m_trace)
LogDebug("Rule Trace,\tRewritePC %s Slot=%u Dst=%u-%u: %s", m_name, m_fromSlot, m_fromIdStart, m_fromIdEnd, ret ? "matched" : "not matched");
return ret;
} }
bool CRewritePC::processNet(CDMRData& data) bool CRewritePC::processNet(CDMRData& data)
{ {
return process(data); bool ret = process(data);
if (m_trace)
LogDebug("Rule Trace,\tRewritePC %s Slot=%u Dst=%u-%u: %s", m_name, m_fromSlot, m_fromIdStart, m_fromIdEnd, ret ? "matched" : "not matched");
return ret;
} }
bool CRewritePC::process(CDMRData& data) bool CRewritePC::process(CDMRData& data)

3
RewritePC.h
View File

@@ -26,7 +26,7 @@
class CRewritePC : public IRewrite { class CRewritePC : public IRewrite {
public: public:
CRewritePC(const char* name, unsigned int fromSlot, unsigned int fromId, unsigned int toSlot, unsigned int toId, unsigned int range); CRewritePC(const char* name, unsigned int fromSlot, unsigned int fromId, unsigned int toSlot, unsigned int toId, unsigned int range, bool trace);
virtual ~CRewritePC(); virtual ~CRewritePC();
virtual bool processRF(CDMRData& data); virtual bool processRF(CDMRData& data);
@@ -39,6 +39,7 @@ private:
unsigned int m_fromIdEnd; unsigned int m_fromIdEnd;
unsigned int m_toSlot; unsigned int m_toSlot;
unsigned int m_toIdStart; unsigned int m_toIdStart;
bool m_trace;
CDMRLC m_lc; CDMRLC m_lc;
CDMREmbeddedData m_embeddedLC; CDMREmbeddedData m_embeddedLC;

17
RewriteSrc.cpp
View File

@@ -25,13 +25,14 @@
#include <cstdio> #include <cstdio>
#include <cassert> #include <cassert>
CRewriteSrc::CRewriteSrc(const char* name, unsigned int fromSlot, unsigned int fromId, unsigned int toSlot, unsigned int toTG, unsigned int range) : CRewriteSrc::CRewriteSrc(const char* name, unsigned int fromSlot, unsigned int fromId, unsigned int toSlot, unsigned int toTG, unsigned int range, bool trace) :
m_name(name), m_name(name),
m_fromSlot(fromSlot), m_fromSlot(fromSlot),
m_fromIdStart(fromId), m_fromIdStart(fromId),
m_fromIdEnd(fromId + range), m_fromIdEnd(fromId + range),
m_toSlot(toSlot), m_toSlot(toSlot),
m_toTG(toTG), m_toTG(toTG),
m_trace(trace),
m_lc(FLCO_GROUP, 0U, toTG), m_lc(FLCO_GROUP, 0U, toTG),
m_embeddedLC() m_embeddedLC()
{ {
@@ -47,12 +48,22 @@ CRewriteSrc::~CRewriteSrc()
bool CRewriteSrc::processRF(CDMRData& data) bool CRewriteSrc::processRF(CDMRData& data)
{ {
return process(data); bool ret = process(data);
if (m_trace)
LogDebug("Rule Trace,\tRewriteSrc %s Slot=%u Src=%u-%u: %s", m_name, m_fromSlot, m_fromIdStart, m_fromIdEnd, ret ? "matched" : "not matched");
return ret;
} }
bool CRewriteSrc::processNet(CDMRData& data) bool CRewriteSrc::processNet(CDMRData& data)
{ {
return process(data); bool ret = process(data);
if (m_trace)
LogDebug("Rule Trace,\tRewriteSrc %s Slot=%u Src=%u-%u: %s", m_name, m_fromSlot, m_fromIdStart, m_fromIdEnd, ret ? "matched" : "not matched");
return ret;
} }
bool CRewriteSrc::process(CDMRData& data) bool CRewriteSrc::process(CDMRData& data)

3
RewriteSrc.h
View File

@@ -26,7 +26,7 @@
class CRewriteSrc : public IRewrite { class CRewriteSrc : public IRewrite {
public: public:
CRewriteSrc(const char* name, unsigned int fromSlot, unsigned int fromId, unsigned int toSlot, unsigned int toTG, unsigned int range); CRewriteSrc(const char* name, unsigned int fromSlot, unsigned int fromId, unsigned int toSlot, unsigned int toTG, unsigned int range, bool trace);
virtual ~CRewriteSrc(); virtual ~CRewriteSrc();
virtual bool processRF(CDMRData& data); virtual bool processRF(CDMRData& data);
@@ -39,6 +39,7 @@ private:
unsigned int m_fromIdEnd; unsigned int m_fromIdEnd;
unsigned int m_toSlot; unsigned int m_toSlot;
unsigned int m_toTG; unsigned int m_toTG;
bool m_trace;
CDMRLC m_lc; CDMRLC m_lc;
CDMREmbeddedData m_embeddedLC; CDMREmbeddedData m_embeddedLC;

18
RewriteTG.cpp
View File

@@ -20,17 +20,19 @@
#include "DMRDefines.h" #include "DMRDefines.h"
#include "DMRFullLC.h" #include "DMRFullLC.h"
#include "Log.h"
#include <cstdio> #include <cstdio>
#include <cassert> #include <cassert>
CRewriteTG::CRewriteTG(const char* name, unsigned int fromSlot, unsigned int fromTG, unsigned int toSlot, unsigned int toTG, unsigned int range) : CRewriteTG::CRewriteTG(const char* name, unsigned int fromSlot, unsigned int fromTG, unsigned int toSlot, unsigned int toTG, unsigned int range, bool trace) :
m_name(name), m_name(name),
m_fromSlot(fromSlot), m_fromSlot(fromSlot),
m_fromTGStart(fromTG), m_fromTGStart(fromTG),
m_fromTGEnd(fromTG + range), m_fromTGEnd(fromTG + range),
m_toSlot(toSlot), m_toSlot(toSlot),
m_toTGStart(toTG), m_toTGStart(toTG),
m_trace(trace),
m_lc(FLCO_GROUP, 0U, toTG), m_lc(FLCO_GROUP, 0U, toTG),
m_embeddedLC() m_embeddedLC()
{ {
@@ -44,12 +46,22 @@ CRewriteTG::~CRewriteTG()
bool CRewriteTG::processRF(CDMRData& data) bool CRewriteTG::processRF(CDMRData& data)
{ {
return process(data); bool ret = process(data);
if (m_trace)
LogDebug("Rule Trace,\tRewriteTG %s Slot=%u Dst=TG%u-TG%u: %s", m_name, m_fromSlot, m_fromTGStart, m_fromTGEnd, ret ? "matched" : "not matched");
return ret;
} }
bool CRewriteTG::processNet(CDMRData& data) bool CRewriteTG::processNet(CDMRData& data)
{ {
return process(data); bool ret = process(data);
if (m_trace)
LogDebug("Rule Trace,\tRewriteTG %s Slot=%u Dst=TG%u-TG%u: %s", m_name, m_fromSlot, m_fromTGStart, m_fromTGEnd, ret ? "matched" : "not matched");
return ret;
} }
bool CRewriteTG::process(CDMRData& data) bool CRewriteTG::process(CDMRData& data)

3
RewriteTG.h
View File

@@ -26,7 +26,7 @@
class CRewriteTG : public IRewrite { class CRewriteTG : public IRewrite {
public: public:
CRewriteTG(const char*name, unsigned int fromSlot, unsigned int fromTG, unsigned int toSlot, unsigned int toTG, unsigned int range); CRewriteTG(const char*name, unsigned int fromSlot, unsigned int fromTG, unsigned int toSlot, unsigned int toTG, unsigned int range, bool trace);
virtual ~CRewriteTG(); virtual ~CRewriteTG();
virtual bool processRF(CDMRData& data); virtual bool processRF(CDMRData& data);
@@ -39,6 +39,7 @@ private:
unsigned int m_fromTGEnd; unsigned int m_fromTGEnd;
unsigned int m_toSlot; unsigned int m_toSlot;
unsigned int m_toTGStart; unsigned int m_toTGStart;
bool m_trace;
CDMRLC m_lc; CDMRLC m_lc;
CDMREmbeddedData m_embeddedLC; CDMREmbeddedData m_embeddedLC;

17
RewriteType.cpp
View File

@@ -25,12 +25,13 @@
#include <cstdio> #include <cstdio>
#include <cassert> #include <cassert>
CRewriteType::CRewriteType(const char* name, unsigned int fromSlot, unsigned int fromTG, unsigned int toSlot, unsigned int toId) : CRewriteType::CRewriteType(const char* name, unsigned int fromSlot, unsigned int fromTG, unsigned int toSlot, unsigned int toId, bool trace) :
m_name(name), m_name(name),
m_fromSlot(fromSlot), m_fromSlot(fromSlot),
m_fromTG(fromTG), m_fromTG(fromTG),
m_toSlot(toSlot), m_toSlot(toSlot),
m_toId(toId), m_toId(toId),
m_trace(trace),
m_lc(FLCO_USER_USER, 0U, toId), m_lc(FLCO_USER_USER, 0U, toId),
m_embeddedLC() m_embeddedLC()
{ {
@@ -44,12 +45,22 @@ CRewriteType::~CRewriteType()
bool CRewriteType::processRF(CDMRData& data) bool CRewriteType::processRF(CDMRData& data)
{ {
return process(data); bool ret = process(data);
if (m_trace)
LogDebug("Rule Trace,\tRewriteType %s Slot=%u Dst=TG%u: %s", m_name, m_fromSlot, m_fromTG, ret ? "matched" : "not matched");
return ret;
} }
bool CRewriteType::processNet(CDMRData& data) bool CRewriteType::processNet(CDMRData& data)
{ {
return process(data); bool ret = process(data);
if (m_trace)
LogDebug("Rule Trace,\tRewriteType %s Slot=%u Dst=TG%u: %s", m_name, m_fromSlot, m_fromTG, ret ? "matched" : "not matched");
return ret;
} }
bool CRewriteType::process(CDMRData& data) bool CRewriteType::process(CDMRData& data)

3
RewriteType.h
View File

@@ -26,7 +26,7 @@
class CRewriteType : public IRewrite { class CRewriteType : public IRewrite {
public: public:
CRewriteType(const char* name, unsigned int fromSlot, unsigned int fromTG, unsigned int toSlot, unsigned int toId); CRewriteType(const char* name, unsigned int fromSlot, unsigned int fromTG, unsigned int toSlot, unsigned int toId, bool trace);
virtual ~CRewriteType(); virtual ~CRewriteType();
virtual bool processRF(CDMRData& data); virtual bool processRF(CDMRData& data);
@@ -38,6 +38,7 @@ private:
unsigned int m_fromTG; unsigned int m_fromTG;
unsigned int m_toSlot; unsigned int m_toSlot;
unsigned int m_toId; unsigned int m_toId;
bool m_trace;
CDMRLC m_lc; CDMRLC m_lc;
CDMREmbeddedData m_embeddedLC; CDMREmbeddedData m_embeddedLC;