MMDVM/DMRGateway
1
0
Fork 0
mirror of https://github.com/g4klx/DMRGateway synced 2025-12-21 13:35:40 +08:00
Code Issues Packages Projects Releases Wiki Activity

First stage of rationalising the rule tracing code.

Browse Source
This commit is contained in:
Jonathan Naylor
2017-06-07 21:22:01 +01:00
parent 06a8b203ce
commit 87bee93b2b
15 changed files with 113 additions and 239 deletions
Download Patch File Download Diff File Expand all files Collapse all files

34
PassAllTG.cpp
View File

@@ -24,10 +24,9 @@
#include <cstdio>
#include <cassert>
CPassAllTG::CPassAllTG(const char* name, unsigned int slot, bool trace) :
CPassAllTG::CPassAllTG(const char* name, unsigned int slot) :
m_name(name),
m_slot(slot),
m_trace(trace)
m_slot(slot)
{
assert(slot == 1U || slot == 2U);
}
@@ -36,30 +35,15 @@ CPassAllTG::~CPassAllTG()
{
}
bool CPassAllTG::processRF(CDMRData& data)
{
bool ret = process(data);
if (m_trace)
LogDebug("Rule Trace,\tPassAllTG %s Slot=%u: %s", m_name, m_slot, ret ? "matched" : "not matched");
return ret;
}
bool CPassAllTG::processNet(CDMRData& data)
{
bool ret = process(data);
if (m_trace)
LogDebug("Rule Trace,\tPassAllTG %s Slot=%u: %s", m_name, m_slot, ret ? "matched" : "not matched");
return ret;
}
bool CPassAllTG::process(CDMRData& data)
bool CPassAllTG::process(CDMRData& data, bool trace)
{
FLCO flco = data.getFLCO();
unsigned int slotNo = data.getSlotNo();
return flco == FLCO_GROUP && slotNo == m_slot;
bool ret = (flco == FLCO_GROUP && slotNo == m_slot);
if (trace)
LogDebug("Rule Trace,\tPassAllTG %s Slot=%u: %s", m_name, m_slot, ret ? "matched" : "not matched");
return ret;
}