mirror of
https://github.com/g4klx/DMRGateway
synced 2026-02-05 13:55:42 +08:00
First stage of rationalising the rule tracing code.
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@@ -25,7 +25,7 @@
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#include <cstdio>
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#include <cassert>
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CRewritePC::CRewritePC(const char* name, unsigned int fromSlot, unsigned int fromId, unsigned int toSlot, unsigned int toId, unsigned int range, bool trace) :
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CRewritePC::CRewritePC(const char* name, unsigned int fromSlot, unsigned int fromId, unsigned int toSlot, unsigned int toId, unsigned int range) :
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m_name(name),
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m_fromSlot(fromSlot),
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m_fromIdStart(fromId),
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@@ -33,7 +33,6 @@ m_fromIdEnd(fromId + range - 1U),
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m_toSlot(toSlot),
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m_toIdStart(toId),
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m_toIdEnd(toId + range - 1U),
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m_trace(trace),
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m_lc(FLCO_USER_USER, 0U, 0U),
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m_embeddedLC()
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{
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@@ -45,40 +44,17 @@ CRewritePC::~CRewritePC()
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{
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}
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bool CRewritePC::processRF(CDMRData& data)
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{
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bool ret = process(data);
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if (m_trace)
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LogDebug("Rule Trace,\tRewritePC from %s Slot=%u Dst=%u-%u: %s", m_name, m_fromSlot, m_fromIdStart, m_fromIdEnd, ret ? "matched" : "not matched");
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if (m_trace && ret)
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LogDebug("Rule Trace,\tRewritePC to %s Slot=%u Dst=%u-%u", m_name, m_toSlot, m_toIdStart, m_toIdEnd);
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return ret;
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}
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bool CRewritePC::processNet(CDMRData& data)
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{
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bool ret = process(data);
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if (m_trace)
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LogDebug("Rule Trace,\tRewritePC from %s Slot=%u Dst=%u-%u: %s", m_name, m_fromSlot, m_fromIdStart, m_fromIdEnd, ret ? "matched" : "not matched");
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if (m_trace && ret)
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LogDebug("Rule Trace,\tRewritePC to %s Slot=%u Dst=%u-%u", m_name, m_toSlot, m_toIdStart, m_toIdEnd);
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return ret;
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}
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bool CRewritePC::process(CDMRData& data)
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bool CRewritePC::process(CDMRData& data, bool trace)
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{
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FLCO flco = data.getFLCO();
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unsigned int dstId = data.getDstId();
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unsigned int slotNo = data.getSlotNo();
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if (flco != FLCO_USER_USER || slotNo != m_fromSlot || dstId < m_fromIdStart || dstId > m_fromIdEnd)
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if (flco != FLCO_USER_USER || slotNo != m_fromSlot || dstId < m_fromIdStart || dstId > m_fromIdEnd) {
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if (trace)
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LogDebug("Rule Trace,\tRewritePC from %s Slot=%u Dst=%u-%u: not matched", m_name, m_fromSlot, m_fromIdStart, m_fromIdEnd);
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return false;
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}
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if (m_fromSlot != m_toSlot)
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data.setSlotNo(m_toSlot);
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@@ -107,6 +83,11 @@ bool CRewritePC::process(CDMRData& data)
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}
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}
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if (trace) {
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LogDebug("Rule Trace,\tRewritePC from %s Slot=%u Dst=%u-%u: not matched", m_name, m_fromSlot, m_fromIdStart, m_fromIdEnd);
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LogDebug("Rule Trace,\tRewritePC to %s Slot=%u Dst=%u-%u", m_name, m_toSlot, m_toIdStart, m_toIdEnd);
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}
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return true;
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}
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