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First stage of rationalising the rule tracing code.

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Jonathan Naylor
2017-06-07 21:22:01 +01:00
parent 06a8b203ce
commit 87bee93b2b
15 changed files with 113 additions and 239 deletions
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45
RewriteTG.cpp
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@@ -25,7 +25,7 @@
#include <cstdio>
#include <cassert>
CRewriteTG::CRewriteTG(const char* name, unsigned int fromSlot, unsigned int fromTG, unsigned int toSlot, unsigned int toTG, unsigned int range, bool trace) :
CRewriteTG::CRewriteTG(const char* name, unsigned int fromSlot, unsigned int fromTG, unsigned int toSlot, unsigned int toTG, unsigned int range) :
m_name(name),
m_fromSlot(fromSlot),
m_fromTGStart(fromTG),
@@ -33,7 +33,6 @@ m_fromTGEnd(fromTG + range - 1U),
m_toSlot(toSlot),
m_toTGStart(toTG),
m_toTGEnd(toTG + range - 1U),
m_trace(trace),
m_lc(FLCO_GROUP, 0U, toTG),
m_embeddedLC()
{
@@ -45,40 +44,17 @@ CRewriteTG::~CRewriteTG()
{
}
bool CRewriteTG::processRF(CDMRData& data)
bool CRewriteTG::process(CDMRData& data, bool trace)
{
bool ret = process(data);
if (m_trace)
LogDebug("Rule Trace,\tRewriteTG from %s Slot=%u Dst=TG%u-TG%u: %s", m_name, m_fromSlot, m_fromTGStart, m_fromTGEnd, ret ? "matched" : "not matched");
if (m_trace && ret)
LogDebug("Rule Trace,\tRewriteTG to %s Slot=%u Dst=TG%u-TG%u", m_name, m_toSlot, m_toTGStart, m_toTGEnd);
return ret;
}
bool CRewriteTG::processNet(CDMRData& data)
{
bool ret = process(data);
if (m_trace)
LogDebug("Rule Trace,\tRewriteTG from %s Slot=%u Dst=TG%u-TG%u: %s", m_name, m_fromSlot, m_fromTGStart, m_fromTGEnd, ret ? "matched" : "not matched");
if (m_trace && ret)
LogDebug("Rule Trace,\tRewriteTG to %s Slot=%u Dst=TG%u-TG%u", m_name, m_toSlot, m_toTGStart, m_toTGEnd);
return ret;
}
bool CRewriteTG::process(CDMRData& data)
{
FLCO flco = data.getFLCO();
unsigned int dstId = data.getDstId();
FLCO flco = data.getFLCO();
unsigned int dstId = data.getDstId();
unsigned int slotNo = data.getSlotNo();
if (flco != FLCO_GROUP || slotNo != m_fromSlot || dstId < m_fromTGStart || dstId > m_fromTGEnd)
if (flco != FLCO_GROUP || slotNo != m_fromSlot || dstId < m_fromTGStart || dstId > m_fromTGEnd) {
if (trace)
LogDebug("Rule Trace,\tRewriteTG from %s Slot=%u Dst=TG%u-TG%u: not matched", m_name, m_fromSlot, m_fromTGStart, m_fromTGEnd);
return false;
}
if (m_fromSlot != m_toSlot)
data.setSlotNo(m_toSlot);
@@ -107,6 +83,11 @@ bool CRewriteTG::process(CDMRData& data)
}
}
if (trace) {
LogDebug("Rule Trace,\tRewriteTG from %s Slot=%u Dst=TG%u-TG%u: matched", m_name, m_fromSlot, m_fromTGStart, m_fromTGEnd);
LogDebug("Rule Trace,\tRewriteTG to %s Slot=%u Dst=TG%u-TG%u", m_name, m_toSlot, m_toTGStart, m_toTGEnd);
}
return true;
}