mirror of
https://github.com/g4klx/DMRGateway
synced 2025-12-21 21:45:39 +08:00
First stage of rationalising the rule tracing code.
This commit is contained in:
Jonathan Naylor
@@ -289,7 +289,6 @@ int CDMRGateway::run()
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}
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if (m_killed) {
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// LogMessage("DMRGateway-%s is exiting on receipt of SIGHUP1", VERSION);
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m_repeater->close();
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delete m_repeater;
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return 0;
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@@ -301,13 +300,13 @@ int CDMRGateway::run()
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LogInfo("Rule trace: %s", ruleTrace ? "yes" : "no");
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if (m_conf.getDMRNetwork1Enabled()) {
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ret = createDMRNetwork1(ruleTrace);
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ret = createDMRNetwork1();
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if (!ret)
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return 1;
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}
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if (m_conf.getDMRNetwork2Enabled()) {
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ret = createDMRNetwork2(ruleTrace);
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ret = createDMRNetwork2();
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if (!ret)
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return 1;
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}
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@@ -431,12 +430,12 @@ int CDMRGateway::run()
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FLCO flco = data.getFLCO();
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if (flco == FLCO_GROUP && slotNo == m_xlx1Slot && dstId == m_xlx1TG) {
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m_xlx1Rewrite->processRF(data);
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m_xlx1Rewrite->process(data, false);
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m_xlxNetwork1->write(data);
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status[slotNo] = DMRGWS_XLXREFLECTOR1;
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timer[slotNo]->start();
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} else if (flco == FLCO_GROUP && slotNo == m_xlx2Slot && dstId == m_xlx2TG) {
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m_xlx2Rewrite->processRF(data);
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m_xlx2Rewrite->process(data, false);
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m_xlxNetwork2->write(data);
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status[slotNo] = DMRGWS_XLXREFLECTOR2;
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timer[slotNo]->start();
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@@ -536,7 +535,7 @@ int CDMRGateway::run()
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if (m_dmrNetwork1 != NULL) {
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// Rewrite the slot and/or TG or neither
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for (std::vector<IRewrite*>::iterator it = m_dmr1RFRewrites.begin(); it != m_dmr1RFRewrites.end(); ++it) {
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bool ret = (*it)->processRF(data);
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bool ret = (*it)->process(data, ruleTrace);
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if (ret) {
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rewritten = true;
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break;
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@@ -556,7 +555,7 @@ int CDMRGateway::run()
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if (m_dmrNetwork2 != NULL) {
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// Rewrite the slot and/or TG or neither
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for (std::vector<IRewrite*>::iterator it = m_dmr2RFRewrites.begin(); it != m_dmr2RFRewrites.end(); ++it) {
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bool ret = (*it)->processRF(data);
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bool ret = (*it)->process(data, ruleTrace);
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if (ret) {
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rewritten = true;
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break;
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@@ -576,7 +575,7 @@ int CDMRGateway::run()
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if (!rewritten) {
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if (m_dmrNetwork1 != NULL) {
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for (std::vector<IRewrite*>::iterator it = m_dmr1Passalls.begin(); it != m_dmr1Passalls.end(); ++it) {
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bool ret = (*it)->processRF(data);
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bool ret = (*it)->process(data, ruleTrace);
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if (ret) {
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rewritten = true;
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break;
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@@ -596,7 +595,7 @@ int CDMRGateway::run()
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if (!rewritten) {
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if (m_dmrNetwork2 != NULL) {
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for (std::vector<IRewrite*>::iterator it = m_dmr2Passalls.begin(); it != m_dmr2Passalls.end(); ++it) {
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bool ret = (*it)->processRF(data);
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bool ret = (*it)->process(data, ruleTrace);
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if (ret) {
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rewritten = true;
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break;
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@@ -622,7 +621,7 @@ int CDMRGateway::run()
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ret = m_xlxNetwork1->read(data);
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if (ret) {
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if (status[m_xlx1Slot] == DMRGWS_NONE || status[m_xlx1Slot] == DMRGWS_XLXREFLECTOR1) {
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bool ret = m_rpt1Rewrite->processNet(data);
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bool ret = m_rpt1Rewrite->process(data, false);
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if (ret) {
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m_repeater->write(data);
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status[m_xlx1Slot] = DMRGWS_XLXREFLECTOR1;
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@@ -641,7 +640,7 @@ int CDMRGateway::run()
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ret = m_xlxNetwork2->read(data);
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if (ret) {
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if (status[m_xlx2Slot] == DMRGWS_NONE || status[m_xlx2Slot] == DMRGWS_XLXREFLECTOR2) {
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bool ret = m_rpt2Rewrite->processNet(data);
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bool ret = m_rpt2Rewrite->process(data, false);
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if (ret) {
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m_repeater->write(data);
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status[m_xlx2Slot] = DMRGWS_XLXREFLECTOR2;
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@@ -671,7 +670,7 @@ int CDMRGateway::run()
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// Rewrite the slot and/or TG or neither
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bool rewritten = false;
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for (std::vector<IRewrite*>::iterator it = m_dmr1NetRewrites.begin(); it != m_dmr1NetRewrites.end(); ++it) {
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bool ret = (*it)->processNet(data);
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bool ret = (*it)->process(data, ruleTrace);
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if (ret) {
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rewritten = true;
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break;
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@@ -709,7 +708,7 @@ int CDMRGateway::run()
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// Rewrite the slot and/or TG or neither
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bool rewritten = false;
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for (std::vector<IRewrite*>::iterator it = m_dmr2NetRewrites.begin(); it != m_dmr2NetRewrites.end(); ++it) {
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bool ret = (*it)->processNet(data);
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bool ret = (*it)->process(data, ruleTrace);
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if (ret) {
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rewritten = true;
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break;
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@@ -869,7 +868,7 @@ bool CDMRGateway::createMMDVM()
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return true;
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}
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bool CDMRGateway::createDMRNetwork1(bool trace)
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bool CDMRGateway::createDMRNetwork1()
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{
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std::string address = m_conf.getDMRNetwork1Address();
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unsigned int port = m_conf.getDMRNetwork1Port();
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@@ -918,8 +917,8 @@ bool CDMRGateway::createDMRNetwork1(bool trace)
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LogInfo(" Rewrite RF: %u:TG%u-TG%u -> %u:TG%u-TG%u", (*it).m_fromSlot, (*it).m_fromTG, (*it).m_fromTG + (*it).m_range - 1U, (*it).m_toSlot, (*it).m_toTG, (*it).m_toTG + (*it).m_range - 1U);
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LogInfo(" Rewrite Net: %u:TG%u-TG%u -> %u:TG%u-TG%u", (*it).m_toSlot, (*it).m_toTG, (*it).m_toTG + (*it).m_range - 1U, (*it).m_fromSlot, (*it).m_fromTG, (*it).m_fromTG + (*it).m_range - 1U);
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CRewriteTG* rfRewrite = new CRewriteTG("DMR-1", (*it).m_fromSlot, (*it).m_fromTG, (*it).m_toSlot, (*it).m_toTG, (*it).m_range, trace);
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CRewriteTG* netRewrite = new CRewriteTG("DMR-1", (*it).m_toSlot, (*it).m_toTG, (*it).m_fromSlot, (*it).m_fromTG, (*it).m_range, trace);
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CRewriteTG* rfRewrite = new CRewriteTG("DMR-1", (*it).m_fromSlot, (*it).m_fromTG, (*it).m_toSlot, (*it).m_toTG, (*it).m_range);
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CRewriteTG* netRewrite = new CRewriteTG("DMR-1", (*it).m_toSlot, (*it).m_toTG, (*it).m_fromSlot, (*it).m_fromTG, (*it).m_range);
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m_dmr1RFRewrites.push_back(rfRewrite);
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m_dmr1NetRewrites.push_back(netRewrite);
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@@ -929,7 +928,7 @@ bool CDMRGateway::createDMRNetwork1(bool trace)
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for (std::vector<CPCRewriteStruct>::const_iterator it = pcRewrites.begin(); it != pcRewrites.end(); ++it) {
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LogInfo(" Rewrite RF: %u:%u-%u -> %u:%u-%u", (*it).m_fromSlot, (*it).m_fromId, (*it).m_fromId + (*it).m_range - 1U, (*it).m_toSlot, (*it).m_toId, (*it).m_toId + (*it).m_range - 1U);
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CRewritePC* rewrite = new CRewritePC("DMR-1", (*it).m_fromSlot, (*it).m_fromId, (*it).m_toSlot, (*it).m_toId, (*it).m_range, trace);
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CRewritePC* rewrite = new CRewritePC("DMR-1", (*it).m_fromSlot, (*it).m_fromId, (*it).m_toSlot, (*it).m_toId, (*it).m_range);
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m_dmr1RFRewrites.push_back(rewrite);
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}
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@@ -938,7 +937,7 @@ bool CDMRGateway::createDMRNetwork1(bool trace)
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for (std::vector<CTypeRewriteStruct>::const_iterator it = typeRewrites.begin(); it != typeRewrites.end(); ++it) {
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LogInfo(" Rewrite RF: %u:TG%u -> %u:%u", (*it).m_fromSlot, (*it).m_fromTG, (*it).m_toSlot, (*it).m_toId);
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CRewriteType* rewrite = new CRewriteType("DMR-1", (*it).m_fromSlot, (*it).m_fromTG, (*it).m_toSlot, (*it).m_toId, trace);
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CRewriteType* rewrite = new CRewriteType("DMR-1", (*it).m_fromSlot, (*it).m_fromTG, (*it).m_toSlot, (*it).m_toId);
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m_dmr1RFRewrites.push_back(rewrite);
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}
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@@ -947,7 +946,7 @@ bool CDMRGateway::createDMRNetwork1(bool trace)
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for (std::vector<CSrcRewriteStruct>::const_iterator it = srcRewrites.begin(); it != srcRewrites.end(); ++it) {
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LogInfo(" Rewrite Net: %u:%u-%u -> %u:TG%u", (*it).m_fromSlot, (*it).m_fromId, (*it).m_fromId + (*it).m_range - 1U, (*it).m_toSlot, (*it).m_toTG);
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CRewriteSrc* rewrite = new CRewriteSrc("DMR-1", (*it).m_fromSlot, (*it).m_fromId, (*it).m_toSlot, (*it).m_toTG, (*it).m_range, trace);
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CRewriteSrc* rewrite = new CRewriteSrc("DMR-1", (*it).m_fromSlot, (*it).m_fromId, (*it).m_toSlot, (*it).m_toTG, (*it).m_range);
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m_dmr1NetRewrites.push_back(rewrite);
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}
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@@ -956,8 +955,8 @@ bool CDMRGateway::createDMRNetwork1(bool trace)
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for (std::vector<unsigned int>::const_iterator it = tgPassAll.begin(); it != tgPassAll.end(); ++it) {
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LogInfo(" Pass All TG: %u", *it);
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CPassAllTG* rfPassAllTG = new CPassAllTG("DMR-1", *it, trace);
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CPassAllTG* netPassAllTG = new CPassAllTG("DMR-1", *it, trace);
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CPassAllTG* rfPassAllTG = new CPassAllTG("DMR-1", *it);
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CPassAllTG* netPassAllTG = new CPassAllTG("DMR-1", *it);
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m_dmr1Passalls.push_back(rfPassAllTG);
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m_dmr1NetRewrites.push_back(netPassAllTG);
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@@ -967,8 +966,8 @@ bool CDMRGateway::createDMRNetwork1(bool trace)
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for (std::vector<unsigned int>::const_iterator it = pcPassAll.begin(); it != pcPassAll.end(); ++it) {
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LogInfo(" Pass All PC: %u", *it);
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CPassAllPC* rfPassAllPC = new CPassAllPC("DMR-1", *it, trace);
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CPassAllPC* netPassAllPC = new CPassAllPC("DMR-1", *it, trace);
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CPassAllPC* rfPassAllPC = new CPassAllPC("DMR-1", *it);
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CPassAllPC* netPassAllPC = new CPassAllPC("DMR-1", *it);
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m_dmr1Passalls.push_back(rfPassAllPC);
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m_dmr1NetRewrites.push_back(netPassAllPC);
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@@ -977,7 +976,7 @@ bool CDMRGateway::createDMRNetwork1(bool trace)
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return true;
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}
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bool CDMRGateway::createDMRNetwork2(bool trace)
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bool CDMRGateway::createDMRNetwork2()
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{
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std::string address = m_conf.getDMRNetwork2Address();
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unsigned int port = m_conf.getDMRNetwork2Port();
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@@ -1026,8 +1025,8 @@ bool CDMRGateway::createDMRNetwork2(bool trace)
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LogInfo(" Rewrite RF: %u:TG%u-TG%u -> %u:TG%u-TG%u", (*it).m_fromSlot, (*it).m_fromTG, (*it).m_fromTG + (*it).m_range - 1U, (*it).m_toSlot, (*it).m_toTG, (*it).m_toTG + (*it).m_range - 1U);
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LogInfo(" Rewrite Net: %u:TG%u-TG%u -> %u:TG%u-TG%u", (*it).m_toSlot, (*it).m_toTG, (*it).m_toTG + (*it).m_range - 1U, (*it).m_fromSlot, (*it).m_fromTG, (*it).m_fromTG + (*it).m_range - 1U);
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CRewriteTG* rfRewrite = new CRewriteTG("DMR-2", (*it).m_fromSlot, (*it).m_fromTG, (*it).m_toSlot, (*it).m_toTG, (*it).m_range, trace);
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CRewriteTG* netRewrite = new CRewriteTG("DMR-2", (*it).m_toSlot, (*it).m_toTG, (*it).m_fromSlot, (*it).m_fromTG, (*it).m_range, trace);
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CRewriteTG* rfRewrite = new CRewriteTG("DMR-2", (*it).m_fromSlot, (*it).m_fromTG, (*it).m_toSlot, (*it).m_toTG, (*it).m_range);
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CRewriteTG* netRewrite = new CRewriteTG("DMR-2", (*it).m_toSlot, (*it).m_toTG, (*it).m_fromSlot, (*it).m_fromTG, (*it).m_range);
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m_dmr2RFRewrites.push_back(rfRewrite);
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m_dmr2NetRewrites.push_back(netRewrite);
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@@ -1037,7 +1036,7 @@ bool CDMRGateway::createDMRNetwork2(bool trace)
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for (std::vector<CPCRewriteStruct>::const_iterator it = pcRewrites.begin(); it != pcRewrites.end(); ++it) {
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LogInfo(" Rewrite RF: %u:%u-%u -> %u:%u-%u", (*it).m_fromSlot, (*it).m_fromId, (*it).m_fromId + (*it).m_range - 1U, (*it).m_toSlot, (*it).m_toId, (*it).m_toId + (*it).m_range - 1U);
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CRewritePC* rewrite = new CRewritePC("DMR-2", (*it).m_fromSlot, (*it).m_fromId, (*it).m_toSlot, (*it).m_toId, (*it).m_range, trace);
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CRewritePC* rewrite = new CRewritePC("DMR-2", (*it).m_fromSlot, (*it).m_fromId, (*it).m_toSlot, (*it).m_toId, (*it).m_range);
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m_dmr2RFRewrites.push_back(rewrite);
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}
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@@ -1046,7 +1045,7 @@ bool CDMRGateway::createDMRNetwork2(bool trace)
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for (std::vector<CTypeRewriteStruct>::const_iterator it = typeRewrites.begin(); it != typeRewrites.end(); ++it) {
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LogInfo(" Rewrite RF: %u:TG%u -> %u:%u", (*it).m_fromSlot, (*it).m_fromTG, (*it).m_toSlot, (*it).m_toId);
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CRewriteType* rewrite = new CRewriteType("DMR-2", (*it).m_fromSlot, (*it).m_fromTG, (*it).m_toSlot, (*it).m_toId, trace);
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CRewriteType* rewrite = new CRewriteType("DMR-2", (*it).m_fromSlot, (*it).m_fromTG, (*it).m_toSlot, (*it).m_toId);
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m_dmr2RFRewrites.push_back(rewrite);
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}
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@@ -1055,7 +1054,7 @@ bool CDMRGateway::createDMRNetwork2(bool trace)
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for (std::vector<CSrcRewriteStruct>::const_iterator it = srcRewrites.begin(); it != srcRewrites.end(); ++it) {
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LogInfo(" Rewrite Net: %u:%u-%u -> %u:TG%u", (*it).m_fromSlot, (*it).m_fromId, (*it).m_fromId + (*it).m_range - 1U, (*it).m_toSlot, (*it).m_toTG);
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CRewriteSrc* rewrite = new CRewriteSrc("DMR-2", (*it).m_fromSlot, (*it).m_fromId, (*it).m_toSlot, (*it).m_toTG, (*it).m_range, trace);
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CRewriteSrc* rewrite = new CRewriteSrc("DMR-2", (*it).m_fromSlot, (*it).m_fromId, (*it).m_toSlot, (*it).m_toTG, (*it).m_range);
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m_dmr2NetRewrites.push_back(rewrite);
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}
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@@ -1064,8 +1063,8 @@ bool CDMRGateway::createDMRNetwork2(bool trace)
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for (std::vector<unsigned int>::const_iterator it = tgPassAll.begin(); it != tgPassAll.end(); ++it) {
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LogInfo(" Pass All TG: %u", *it);
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CPassAllTG* rfPassAllTG = new CPassAllTG("DMR-2", *it, trace);
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CPassAllTG* netPassAllTG = new CPassAllTG("DMR-2", *it, trace);
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CPassAllTG* rfPassAllTG = new CPassAllTG("DMR-2", *it);
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CPassAllTG* netPassAllTG = new CPassAllTG("DMR-2", *it);
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m_dmr2Passalls.push_back(rfPassAllTG);
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m_dmr2NetRewrites.push_back(netPassAllTG);
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@@ -1075,8 +1074,8 @@ bool CDMRGateway::createDMRNetwork2(bool trace)
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for (std::vector<unsigned int>::const_iterator it = pcPassAll.begin(); it != pcPassAll.end(); ++it) {
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LogInfo(" Pass All PC: %u", *it);
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CPassAllPC* rfPassAllPC = new CPassAllPC("DMR-2", *it, trace);
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CPassAllPC* netPassAllPC = new CPassAllPC("DMR-2", *it, trace);
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CPassAllPC* rfPassAllPC = new CPassAllPC("DMR-2", *it);
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CPassAllPC* netPassAllPC = new CPassAllPC("DMR-2", *it);
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m_dmr2Passalls.push_back(rfPassAllPC);
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m_dmr2NetRewrites.push_back(netPassAllPC);
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@@ -1137,8 +1136,8 @@ bool CDMRGateway::createXLXNetwork1()
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if (m_xlx1Startup != 4000U)
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LogInfo(" Startup: %u", m_xlx1Startup);
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m_rpt1Rewrite = new CRewriteTG("XLX-1", XLX_SLOT, XLX_TG, m_xlx1Slot, m_xlx1TG, 1U, false);
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m_xlx1Rewrite = new CRewriteTG("XLX-1", m_xlx1Slot, m_xlx1TG, XLX_SLOT, XLX_TG, 1U, false);
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m_rpt1Rewrite = new CRewriteTG("XLX-1", XLX_SLOT, XLX_TG, m_xlx1Slot, m_xlx1TG, 1U);
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m_xlx1Rewrite = new CRewriteTG("XLX-1", m_xlx1Slot, m_xlx1TG, XLX_SLOT, XLX_TG, 1U);
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return true;
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}
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@@ -1195,8 +1194,8 @@ bool CDMRGateway::createXLXNetwork2()
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if (m_xlx2Startup != 4000U)
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LogInfo(" Startup: %u", m_xlx2Startup);
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m_rpt2Rewrite = new CRewriteTG("XLX-2", XLX_SLOT, XLX_TG, m_xlx2Slot, m_xlx2TG, 1U, false);
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m_xlx2Rewrite = new CRewriteTG("XLX-2", m_xlx2Slot, m_xlx2TG, XLX_SLOT, XLX_TG, 1U, false);
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m_rpt2Rewrite = new CRewriteTG("XLX-2", XLX_SLOT, XLX_TG, m_xlx2Slot, m_xlx2TG, 1U);
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m_xlx2Rewrite = new CRewriteTG("XLX-2", m_xlx2Slot, m_xlx2TG, XLX_SLOT, XLX_TG, 1U);
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return true;
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}
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@@ -69,8 +69,8 @@ private:
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std::vector<IRewrite*> m_dmr2Passalls;
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bool createMMDVM();
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bool createDMRNetwork1(bool trace);
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bool createDMRNetwork2(bool trace);
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bool createDMRNetwork1();
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bool createDMRNetwork2();
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bool createXLXNetwork1();
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bool createXLXNetwork2();
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void writeXLXLink(unsigned int srcId, unsigned int dstId, CDMRNetwork* network);
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@@ -24,10 +24,9 @@
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#include <cstdio>
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#include <cassert>
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CPassAllPC::CPassAllPC(const char* name, unsigned int slot, bool trace) :
|
||||
CPassAllPC::CPassAllPC(const char* name, unsigned int slot) :
|
||||
m_name(name),
|
||||
m_slot(slot),
|
||||
m_trace(trace)
|
||||
m_slot(slot)
|
||||
{
|
||||
assert(slot == 1U || slot == 2U);
|
||||
}
|
||||
@@ -36,30 +35,15 @@ CPassAllPC::~CPassAllPC()
|
||||
{
|
||||
}
|
||||
|
||||
bool CPassAllPC::processRF(CDMRData& data)
|
||||
{
|
||||
bool ret = process(data);
|
||||
|
||||
if (m_trace)
|
||||
LogDebug("Rule Trace,\tPassAllPC %s Slot=%u: %s", m_name, m_slot, ret ? "matched" : "not matched");
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
bool CPassAllPC::processNet(CDMRData& data)
|
||||
{
|
||||
bool ret = process(data);
|
||||
|
||||
if (m_trace)
|
||||
LogDebug("Rule Trace,\tPassAllPC %s Slot=%u: %s", m_name, m_slot, ret ? "matched" : "not matched");
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
bool CPassAllPC::process(CDMRData& data)
|
||||
bool CPassAllPC::process(CDMRData& data, bool trace)
|
||||
{
|
||||
FLCO flco = data.getFLCO();
|
||||
unsigned int slotNo = data.getSlotNo();
|
||||
|
||||
return flco == FLCO_USER_USER && slotNo == m_slot;
|
||||
bool ret = (flco == FLCO_USER_USER && slotNo == m_slot);
|
||||
|
||||
if (trace)
|
||||
LogDebug("Rule Trace,\tPassAllPC %s Slot=%u: %s", m_name, m_slot, ret ? "matched" : "not matched");
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
@@ -24,18 +24,14 @@
|
||||
|
||||
class CPassAllPC : public IRewrite {
|
||||
public:
|
||||
CPassAllPC(const char* name, unsigned int slot, bool trace);
|
||||
CPassAllPC(const char* name, unsigned int slot);
|
||||
virtual ~CPassAllPC();
|
||||
|
||||
virtual bool processRF(CDMRData& data);
|
||||
virtual bool processNet(CDMRData& data);
|
||||
virtual bool process(CDMRData& data, bool trace);
|
||||
|
||||
private:
|
||||
const char* m_name;
|
||||
unsigned int m_slot;
|
||||
bool m_trace;
|
||||
|
||||
bool process(CDMRData& data);
|
||||
};
|
||||
|
||||
|
||||
|
||||
@@ -24,10 +24,9 @@
|
||||
#include <cstdio>
|
||||
#include <cassert>
|
||||
|
||||
CPassAllTG::CPassAllTG(const char* name, unsigned int slot, bool trace) :
|
||||
CPassAllTG::CPassAllTG(const char* name, unsigned int slot) :
|
||||
m_name(name),
|
||||
m_slot(slot),
|
||||
m_trace(trace)
|
||||
m_slot(slot)
|
||||
{
|
||||
assert(slot == 1U || slot == 2U);
|
||||
}
|
||||
@@ -36,30 +35,15 @@ CPassAllTG::~CPassAllTG()
|
||||
{
|
||||
}
|
||||
|
||||
bool CPassAllTG::processRF(CDMRData& data)
|
||||
{
|
||||
bool ret = process(data);
|
||||
|
||||
if (m_trace)
|
||||
LogDebug("Rule Trace,\tPassAllTG %s Slot=%u: %s", m_name, m_slot, ret ? "matched" : "not matched");
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
bool CPassAllTG::processNet(CDMRData& data)
|
||||
{
|
||||
bool ret = process(data);
|
||||
|
||||
if (m_trace)
|
||||
LogDebug("Rule Trace,\tPassAllTG %s Slot=%u: %s", m_name, m_slot, ret ? "matched" : "not matched");
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
bool CPassAllTG::process(CDMRData& data)
|
||||
bool CPassAllTG::process(CDMRData& data, bool trace)
|
||||
{
|
||||
FLCO flco = data.getFLCO();
|
||||
unsigned int slotNo = data.getSlotNo();
|
||||
|
||||
return flco == FLCO_GROUP && slotNo == m_slot;
|
||||
bool ret = (flco == FLCO_GROUP && slotNo == m_slot);
|
||||
|
||||
if (trace)
|
||||
LogDebug("Rule Trace,\tPassAllTG %s Slot=%u: %s", m_name, m_slot, ret ? "matched" : "not matched");
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
@@ -24,18 +24,14 @@
|
||||
|
||||
class CPassAllTG : public IRewrite {
|
||||
public:
|
||||
CPassAllTG(const char* name, unsigned int slot, bool trace);
|
||||
CPassAllTG(const char* name, unsigned int slot);
|
||||
virtual ~CPassAllTG();
|
||||
|
||||
virtual bool processRF(CDMRData& data);
|
||||
virtual bool processNet(CDMRData& data);
|
||||
virtual bool process(CDMRData& data, bool trace);
|
||||
|
||||
private:
|
||||
const char* m_name;
|
||||
unsigned int m_slot;
|
||||
bool m_trace;
|
||||
|
||||
bool process(CDMRData& data);
|
||||
};
|
||||
|
||||
|
||||
|
||||
@@ -25,8 +25,7 @@ class IRewrite {
|
||||
public:
|
||||
virtual ~IRewrite() = 0;
|
||||
|
||||
virtual bool processRF(CDMRData& data) = 0;
|
||||
virtual bool processNet(CDMRData& data) = 0;
|
||||
virtual bool process(CDMRData& data, bool trace) = 0;
|
||||
|
||||
private:
|
||||
};
|
||||
|
||||
@@ -25,7 +25,7 @@
|
||||
#include <cstdio>
|
||||
#include <cassert>
|
||||
|
||||
CRewritePC::CRewritePC(const char* name, unsigned int fromSlot, unsigned int fromId, unsigned int toSlot, unsigned int toId, unsigned int range, bool trace) :
|
||||
CRewritePC::CRewritePC(const char* name, unsigned int fromSlot, unsigned int fromId, unsigned int toSlot, unsigned int toId, unsigned int range) :
|
||||
m_name(name),
|
||||
m_fromSlot(fromSlot),
|
||||
m_fromIdStart(fromId),
|
||||
@@ -33,7 +33,6 @@ m_fromIdEnd(fromId + range - 1U),
|
||||
m_toSlot(toSlot),
|
||||
m_toIdStart(toId),
|
||||
m_toIdEnd(toId + range - 1U),
|
||||
m_trace(trace),
|
||||
m_lc(FLCO_USER_USER, 0U, 0U),
|
||||
m_embeddedLC()
|
||||
{
|
||||
@@ -45,40 +44,17 @@ CRewritePC::~CRewritePC()
|
||||
{
|
||||
}
|
||||
|
||||
bool CRewritePC::processRF(CDMRData& data)
|
||||
{
|
||||
bool ret = process(data);
|
||||
|
||||
if (m_trace)
|
||||
LogDebug("Rule Trace,\tRewritePC from %s Slot=%u Dst=%u-%u: %s", m_name, m_fromSlot, m_fromIdStart, m_fromIdEnd, ret ? "matched" : "not matched");
|
||||
|
||||
if (m_trace && ret)
|
||||
LogDebug("Rule Trace,\tRewritePC to %s Slot=%u Dst=%u-%u", m_name, m_toSlot, m_toIdStart, m_toIdEnd);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
bool CRewritePC::processNet(CDMRData& data)
|
||||
{
|
||||
bool ret = process(data);
|
||||
|
||||
if (m_trace)
|
||||
LogDebug("Rule Trace,\tRewritePC from %s Slot=%u Dst=%u-%u: %s", m_name, m_fromSlot, m_fromIdStart, m_fromIdEnd, ret ? "matched" : "not matched");
|
||||
|
||||
if (m_trace && ret)
|
||||
LogDebug("Rule Trace,\tRewritePC to %s Slot=%u Dst=%u-%u", m_name, m_toSlot, m_toIdStart, m_toIdEnd);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
bool CRewritePC::process(CDMRData& data)
|
||||
bool CRewritePC::process(CDMRData& data, bool trace)
|
||||
{
|
||||
FLCO flco = data.getFLCO();
|
||||
unsigned int dstId = data.getDstId();
|
||||
unsigned int slotNo = data.getSlotNo();
|
||||
|
||||
if (flco != FLCO_USER_USER || slotNo != m_fromSlot || dstId < m_fromIdStart || dstId > m_fromIdEnd)
|
||||
if (flco != FLCO_USER_USER || slotNo != m_fromSlot || dstId < m_fromIdStart || dstId > m_fromIdEnd) {
|
||||
if (trace)
|
||||
LogDebug("Rule Trace,\tRewritePC from %s Slot=%u Dst=%u-%u: not matched", m_name, m_fromSlot, m_fromIdStart, m_fromIdEnd);
|
||||
return false;
|
||||
}
|
||||
|
||||
if (m_fromSlot != m_toSlot)
|
||||
data.setSlotNo(m_toSlot);
|
||||
@@ -107,6 +83,11 @@ bool CRewritePC::process(CDMRData& data)
|
||||
}
|
||||
}
|
||||
|
||||
if (trace) {
|
||||
LogDebug("Rule Trace,\tRewritePC from %s Slot=%u Dst=%u-%u: not matched", m_name, m_fromSlot, m_fromIdStart, m_fromIdEnd);
|
||||
LogDebug("Rule Trace,\tRewritePC to %s Slot=%u Dst=%u-%u", m_name, m_toSlot, m_toIdStart, m_toIdEnd);
|
||||
}
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
|
||||
@@ -26,11 +26,10 @@
|
||||
|
||||
class CRewritePC : public IRewrite {
|
||||
public:
|
||||
CRewritePC(const char* name, unsigned int fromSlot, unsigned int fromId, unsigned int toSlot, unsigned int toId, unsigned int range, bool trace);
|
||||
CRewritePC(const char* name, unsigned int fromSlot, unsigned int fromId, unsigned int toSlot, unsigned int toId, unsigned int range);
|
||||
virtual ~CRewritePC();
|
||||
|
||||
virtual bool processRF(CDMRData& data);
|
||||
virtual bool processNet(CDMRData& data);
|
||||
virtual bool process(CDMRData& data, bool trace);
|
||||
|
||||
private:
|
||||
const char* m_name;
|
||||
@@ -40,11 +39,9 @@ private:
|
||||
unsigned int m_toSlot;
|
||||
unsigned int m_toIdStart;
|
||||
unsigned int m_toIdEnd;
|
||||
bool m_trace;
|
||||
CDMRLC m_lc;
|
||||
CDMREmbeddedData m_embeddedLC;
|
||||
|
||||
bool process(CDMRData& data);
|
||||
void processHeader(CDMRData& data, unsigned int dstId, unsigned char dataType);
|
||||
void processVoice(CDMRData& data, unsigned int dstId);
|
||||
};
|
||||
|
||||
@@ -25,14 +25,13 @@
|
||||
#include <cstdio>
|
||||
#include <cassert>
|
||||
|
||||
CRewriteSrc::CRewriteSrc(const char* name, unsigned int fromSlot, unsigned int fromId, unsigned int toSlot, unsigned int toTG, unsigned int range, bool trace) :
|
||||
CRewriteSrc::CRewriteSrc(const char* name, unsigned int fromSlot, unsigned int fromId, unsigned int toSlot, unsigned int toTG, unsigned int range) :
|
||||
m_name(name),
|
||||
m_fromSlot(fromSlot),
|
||||
m_fromIdStart(fromId),
|
||||
m_fromIdEnd(fromId + range - 1U),
|
||||
m_toSlot(toSlot),
|
||||
m_toTG(toTG),
|
||||
m_trace(trace),
|
||||
m_lc(FLCO_GROUP, 0U, toTG),
|
||||
m_embeddedLC()
|
||||
{
|
||||
@@ -46,40 +45,17 @@ CRewriteSrc::~CRewriteSrc()
|
||||
{
|
||||
}
|
||||
|
||||
bool CRewriteSrc::processRF(CDMRData& data)
|
||||
{
|
||||
bool ret = process(data);
|
||||
|
||||
if (m_trace)
|
||||
LogDebug("Rule Trace,\tRewriteSrc from %s Slot=%u Src=%u-%u: %s", m_name, m_fromSlot, m_fromIdStart, m_fromIdEnd, ret ? "matched" : "not matched");
|
||||
|
||||
if (m_trace && ret)
|
||||
LogDebug("Rule Trace,\tRewriteSrc to %s Slot=%u Dst=TG%u", m_name, m_toSlot, m_toTG);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
bool CRewriteSrc::processNet(CDMRData& data)
|
||||
{
|
||||
bool ret = process(data);
|
||||
|
||||
if (m_trace)
|
||||
LogDebug("Rule Trace,\tRewriteSrc from %s Slot=%u Src=%u-%u: %s", m_name, m_fromSlot, m_fromIdStart, m_fromIdEnd, ret ? "matched" : "not matched");
|
||||
|
||||
if (m_trace && ret)
|
||||
LogDebug("Rule Trace,\tRewriteSrc to %s Slot=%u Dst=TG%u", m_name, m_toSlot, m_toTG);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
bool CRewriteSrc::process(CDMRData& data)
|
||||
bool CRewriteSrc::process(CDMRData& data, bool trace)
|
||||
{
|
||||
FLCO flco = data.getFLCO();
|
||||
unsigned int srcId = data.getSrcId();
|
||||
unsigned int slotNo = data.getSlotNo();
|
||||
|
||||
if (flco != FLCO_USER_USER || slotNo != m_fromSlot || srcId < m_fromIdStart || srcId > m_fromIdEnd)
|
||||
if (flco != FLCO_USER_USER || slotNo != m_fromSlot || srcId < m_fromIdStart || srcId > m_fromIdEnd) {
|
||||
if (trace)
|
||||
LogDebug("Rule Trace,\tRewriteSrc from %s Slot=%u Src=%u-%u: not matched", m_name, m_fromSlot, m_fromIdStart, m_fromIdEnd);
|
||||
return false;
|
||||
}
|
||||
|
||||
if (m_fromSlot != m_toSlot)
|
||||
data.setSlotNo(m_toSlot);
|
||||
@@ -105,6 +81,11 @@ bool CRewriteSrc::process(CDMRData& data)
|
||||
break;
|
||||
}
|
||||
|
||||
if (trace) {
|
||||
LogDebug("Rule Trace,\tRewriteSrc from %s Slot=%u Src=%u-%u: matched", m_name, m_fromSlot, m_fromIdStart, m_fromIdEnd);
|
||||
LogDebug("Rule Trace,\tRewriteSrc to %s Slot=%u Dst=TG%u", m_name, m_toSlot, m_toTG);
|
||||
}
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
|
||||
@@ -26,11 +26,10 @@
|
||||
|
||||
class CRewriteSrc : public IRewrite {
|
||||
public:
|
||||
CRewriteSrc(const char* name, unsigned int fromSlot, unsigned int fromId, unsigned int toSlot, unsigned int toTG, unsigned int range, bool trace);
|
||||
CRewriteSrc(const char* name, unsigned int fromSlot, unsigned int fromId, unsigned int toSlot, unsigned int toTG, unsigned int range);
|
||||
virtual ~CRewriteSrc();
|
||||
|
||||
virtual bool processRF(CDMRData& data);
|
||||
virtual bool processNet(CDMRData& data);
|
||||
virtual bool process(CDMRData& data, bool trace);
|
||||
|
||||
private:
|
||||
const char* m_name;
|
||||
@@ -39,11 +38,9 @@ private:
|
||||
unsigned int m_fromIdEnd;
|
||||
unsigned int m_toSlot;
|
||||
unsigned int m_toTG;
|
||||
bool m_trace;
|
||||
CDMRLC m_lc;
|
||||
CDMREmbeddedData m_embeddedLC;
|
||||
|
||||
bool process(CDMRData& data);
|
||||
void processHeader(CDMRData& data, unsigned char dataType);
|
||||
void processVoice(CDMRData& data);
|
||||
};
|
||||
|
||||
@@ -25,7 +25,7 @@
|
||||
#include <cstdio>
|
||||
#include <cassert>
|
||||
|
||||
CRewriteTG::CRewriteTG(const char* name, unsigned int fromSlot, unsigned int fromTG, unsigned int toSlot, unsigned int toTG, unsigned int range, bool trace) :
|
||||
CRewriteTG::CRewriteTG(const char* name, unsigned int fromSlot, unsigned int fromTG, unsigned int toSlot, unsigned int toTG, unsigned int range) :
|
||||
m_name(name),
|
||||
m_fromSlot(fromSlot),
|
||||
m_fromTGStart(fromTG),
|
||||
@@ -33,7 +33,6 @@ m_fromTGEnd(fromTG + range - 1U),
|
||||
m_toSlot(toSlot),
|
||||
m_toTGStart(toTG),
|
||||
m_toTGEnd(toTG + range - 1U),
|
||||
m_trace(trace),
|
||||
m_lc(FLCO_GROUP, 0U, toTG),
|
||||
m_embeddedLC()
|
||||
{
|
||||
@@ -45,40 +44,17 @@ CRewriteTG::~CRewriteTG()
|
||||
{
|
||||
}
|
||||
|
||||
bool CRewriteTG::processRF(CDMRData& data)
|
||||
{
|
||||
bool ret = process(data);
|
||||
|
||||
if (m_trace)
|
||||
LogDebug("Rule Trace,\tRewriteTG from %s Slot=%u Dst=TG%u-TG%u: %s", m_name, m_fromSlot, m_fromTGStart, m_fromTGEnd, ret ? "matched" : "not matched");
|
||||
|
||||
if (m_trace && ret)
|
||||
LogDebug("Rule Trace,\tRewriteTG to %s Slot=%u Dst=TG%u-TG%u", m_name, m_toSlot, m_toTGStart, m_toTGEnd);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
bool CRewriteTG::processNet(CDMRData& data)
|
||||
{
|
||||
bool ret = process(data);
|
||||
|
||||
if (m_trace)
|
||||
LogDebug("Rule Trace,\tRewriteTG from %s Slot=%u Dst=TG%u-TG%u: %s", m_name, m_fromSlot, m_fromTGStart, m_fromTGEnd, ret ? "matched" : "not matched");
|
||||
|
||||
if (m_trace && ret)
|
||||
LogDebug("Rule Trace,\tRewriteTG to %s Slot=%u Dst=TG%u-TG%u", m_name, m_toSlot, m_toTGStart, m_toTGEnd);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
bool CRewriteTG::process(CDMRData& data)
|
||||
bool CRewriteTG::process(CDMRData& data, bool trace)
|
||||
{
|
||||
FLCO flco = data.getFLCO();
|
||||
unsigned int dstId = data.getDstId();
|
||||
unsigned int slotNo = data.getSlotNo();
|
||||
|
||||
if (flco != FLCO_GROUP || slotNo != m_fromSlot || dstId < m_fromTGStart || dstId > m_fromTGEnd)
|
||||
if (flco != FLCO_GROUP || slotNo != m_fromSlot || dstId < m_fromTGStart || dstId > m_fromTGEnd) {
|
||||
if (trace)
|
||||
LogDebug("Rule Trace,\tRewriteTG from %s Slot=%u Dst=TG%u-TG%u: not matched", m_name, m_fromSlot, m_fromTGStart, m_fromTGEnd);
|
||||
return false;
|
||||
}
|
||||
|
||||
if (m_fromSlot != m_toSlot)
|
||||
data.setSlotNo(m_toSlot);
|
||||
@@ -107,6 +83,11 @@ bool CRewriteTG::process(CDMRData& data)
|
||||
}
|
||||
}
|
||||
|
||||
if (trace) {
|
||||
LogDebug("Rule Trace,\tRewriteTG from %s Slot=%u Dst=TG%u-TG%u: matched", m_name, m_fromSlot, m_fromTGStart, m_fromTGEnd);
|
||||
LogDebug("Rule Trace,\tRewriteTG to %s Slot=%u Dst=TG%u-TG%u", m_name, m_toSlot, m_toTGStart, m_toTGEnd);
|
||||
}
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
|
||||
@@ -26,11 +26,10 @@
|
||||
|
||||
class CRewriteTG : public IRewrite {
|
||||
public:
|
||||
CRewriteTG(const char*name, unsigned int fromSlot, unsigned int fromTG, unsigned int toSlot, unsigned int toTG, unsigned int range, bool trace);
|
||||
CRewriteTG(const char*name, unsigned int fromSlot, unsigned int fromTG, unsigned int toSlot, unsigned int toTG, unsigned int range);
|
||||
virtual ~CRewriteTG();
|
||||
|
||||
virtual bool processRF(CDMRData& data);
|
||||
virtual bool processNet(CDMRData& data);
|
||||
virtual bool process(CDMRData& data, bool trace);
|
||||
|
||||
private:
|
||||
const char* m_name;
|
||||
@@ -40,11 +39,9 @@ private:
|
||||
unsigned int m_toSlot;
|
||||
unsigned int m_toTGStart;
|
||||
unsigned int m_toTGEnd;
|
||||
bool m_trace;
|
||||
CDMRLC m_lc;
|
||||
CDMREmbeddedData m_embeddedLC;
|
||||
|
||||
bool process(CDMRData& data);
|
||||
void processHeader(CDMRData& data, unsigned int tg, unsigned char dataType);
|
||||
void processVoice(CDMRData& data, unsigned int tg);
|
||||
};
|
||||
|
||||
@@ -25,13 +25,12 @@
|
||||
#include <cstdio>
|
||||
#include <cassert>
|
||||
|
||||
CRewriteType::CRewriteType(const char* name, unsigned int fromSlot, unsigned int fromTG, unsigned int toSlot, unsigned int toId, bool trace) :
|
||||
CRewriteType::CRewriteType(const char* name, unsigned int fromSlot, unsigned int fromTG, unsigned int toSlot, unsigned int toId) :
|
||||
m_name(name),
|
||||
m_fromSlot(fromSlot),
|
||||
m_fromTG(fromTG),
|
||||
m_toSlot(toSlot),
|
||||
m_toId(toId),
|
||||
m_trace(trace),
|
||||
m_lc(FLCO_USER_USER, 0U, toId),
|
||||
m_embeddedLC()
|
||||
{
|
||||
@@ -43,34 +42,17 @@ CRewriteType::~CRewriteType()
|
||||
{
|
||||
}
|
||||
|
||||
bool CRewriteType::processRF(CDMRData& data)
|
||||
{
|
||||
bool ret = process(data);
|
||||
|
||||
if (m_trace)
|
||||
LogDebug("Rule Trace,\tRewriteType %s Slot=%u Dst=TG%u: %s", m_name, m_fromSlot, m_fromTG, ret ? "matched" : "not matched");
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
bool CRewriteType::processNet(CDMRData& data)
|
||||
{
|
||||
bool ret = process(data);
|
||||
|
||||
if (m_trace)
|
||||
LogDebug("Rule Trace,\tRewriteType %s Slot=%u Dst=TG%u: %s", m_name, m_fromSlot, m_fromTG, ret ? "matched" : "not matched");
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
bool CRewriteType::process(CDMRData& data)
|
||||
bool CRewriteType::process(CDMRData& data, bool trace)
|
||||
{
|
||||
FLCO flco = data.getFLCO();
|
||||
unsigned int dstId = data.getDstId();
|
||||
unsigned int slotNo = data.getSlotNo();
|
||||
|
||||
if (flco != FLCO_GROUP || slotNo != m_fromSlot || dstId != m_fromTG)
|
||||
if (flco != FLCO_GROUP || slotNo != m_fromSlot || dstId != m_fromTG) {
|
||||
if (trace)
|
||||
LogDebug("Rule Trace,\tRewriteType %s Slot=%u Dst=TG%u: not matched", m_name, m_fromSlot, m_fromTG);
|
||||
return false;
|
||||
}
|
||||
|
||||
if (m_fromSlot != m_toSlot)
|
||||
data.setSlotNo(m_toSlot);
|
||||
@@ -96,6 +78,9 @@ bool CRewriteType::process(CDMRData& data)
|
||||
break;
|
||||
}
|
||||
|
||||
if (trace)
|
||||
LogDebug("Rule Trace,\tRewriteType %s Slot=%u Dst=TG%u: matched", m_name, m_fromSlot, m_fromTG);
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
|
||||
@@ -26,11 +26,10 @@
|
||||
|
||||
class CRewriteType : public IRewrite {
|
||||
public:
|
||||
CRewriteType(const char* name, unsigned int fromSlot, unsigned int fromTG, unsigned int toSlot, unsigned int toId, bool trace);
|
||||
CRewriteType(const char* name, unsigned int fromSlot, unsigned int fromTG, unsigned int toSlot, unsigned int toId);
|
||||
virtual ~CRewriteType();
|
||||
|
||||
virtual bool processRF(CDMRData& data);
|
||||
virtual bool processNet(CDMRData& data);
|
||||
virtual bool process(CDMRData& data, bool trace);
|
||||
|
||||
private:
|
||||
const char* m_name;
|
||||
@@ -38,11 +37,9 @@ private:
|
||||
unsigned int m_fromTG;
|
||||
unsigned int m_toSlot;
|
||||
unsigned int m_toId;
|
||||
bool m_trace;
|
||||
CDMRLC m_lc;
|
||||
CDMREmbeddedData m_embeddedLC;
|
||||
|
||||
bool process(CDMRData& data);
|
||||
void processHeader(CDMRData& data, unsigned char dataType);
|
||||
void processVoice(CDMRData& data);
|
||||
};
|
||||
|
||||
Reference in New Issue
Block a user