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https://github.com/g4klx/DMRGateway
synced 2025-12-20 21:25:37 +08:00
Suppress smae TGs in rule tracer
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@@ -51,8 +51,12 @@ bool CRewriteTG::process(CDMRData& data, bool trace)
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unsigned int slotNo = data.getSlotNo();
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if (flco != FLCO_GROUP || slotNo != m_fromSlot || dstId < m_fromTGStart || dstId > m_fromTGEnd) {
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if (trace)
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LogDebug("Rule Trace,\tRewriteTG from %s Slot=%u Dst=TG%u-TG%u: not matched", m_name, m_fromSlot, m_fromTGStart, m_fromTGEnd);
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if (trace) {
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if (m_fromTGStart == m_fromTGEnd)
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LogDebug("Rule Trace,\tRewriteTG from %s Slot=%u Dst=TG%u: not matched", m_name, m_fromSlot, m_fromTGStart);
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else
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LogDebug("Rule Trace,\tRewriteTG from %s Slot=%u Dst=TG%u-TG%u: not matched", m_name, m_fromSlot, m_fromTGStart, m_fromTGEnd);
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}
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return false;
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}
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@@ -84,8 +88,14 @@ bool CRewriteTG::process(CDMRData& data, bool trace)
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}
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if (trace) {
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LogDebug("Rule Trace,\tRewriteTG from %s Slot=%u Dst=TG%u-TG%u: matched", m_name, m_fromSlot, m_fromTGStart, m_fromTGEnd);
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LogDebug("Rule Trace,\tRewriteTG to %s Slot=%u Dst=TG%u-TG%u", m_name, m_toSlot, m_toTGStart, m_toTGEnd);
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if (m_fromTGStart == m_fromTGEnd)
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LogDebug("Rule Trace,\tRewriteTG from %s Slot=%u Dst=TG%u: matched", m_name, m_fromSlot, m_fromTGStart);
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else
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LogDebug("Rule Trace,\tRewriteTG from %s Slot=%u Dst=TG%u-TG%u: matched", m_name, m_fromSlot, m_fromTGStart, m_fromTGEnd);
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if (m_toTGStart == m_toTGEnd)
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LogDebug("Rule Trace,\tRewriteTG to %s Slot=%u Dst=TG%u", m_name, m_toSlot, m_toTGStart);
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else
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LogDebug("Rule Trace,\tRewriteTG to %s Slot=%u Dst=TG%u-TG%u", m_name, m_toSlot, m_toTGStart, m_toTGEnd);
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}
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return true;
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