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Add an extra trace line when matched to say where rewritten to

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g0wfv
2017-06-07 13:15:17 +01:00
parent 2d670d330b
commit e4b3f2b6cb
5 changed files with 28 additions and 6 deletions
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11
RewritePC.cpp
View File

@@ -32,6 +32,7 @@ m_fromIdStart(fromId),
m_fromIdEnd(fromId + range - 1U),
m_toSlot(toSlot),
m_toIdStart(toId),
m_toIdEnd(toId + range - 1U),
m_trace(trace),
m_lc(FLCO_USER_USER, 0U, 0U),
m_embeddedLC()
@@ -49,7 +50,10 @@ bool CRewritePC::processRF(CDMRData& data)
bool ret = process(data);
if (m_trace)
LogDebug("Rule Trace,\tRewritePC %s Slot=%u Dst=%u-%u: %s", m_name, m_fromSlot, m_fromIdStart, m_fromIdEnd, ret ? "matched" : "not matched");
LogDebug("Rule Trace,\tRewritePC from %s Slot=%u Dst=%u-%u: %s", m_name, m_fromSlot, m_fromIdStart, m_fromIdEnd, ret ? "matched" : "not matched");
if (m_trace && ret)
LogDebug("Rule Trace,\tRewritePC to %s Slot=%u Dst=%u-%u", m_name, m_toSlot, m_toIdStart, m_toIdEnd);
return ret;
}
@@ -59,7 +63,10 @@ bool CRewritePC::processNet(CDMRData& data)
bool ret = process(data);
if (m_trace)
LogDebug("Rule Trace,\tRewritePC %s Slot=%u Dst=%u-%u: %s", m_name, m_fromSlot, m_fromIdStart, m_fromIdEnd, ret ? "matched" : "not matched");
LogDebug("Rule Trace,\tRewritePC from %s Slot=%u Dst=%u-%u: %s", m_name, m_fromSlot, m_fromIdStart, m_fromIdEnd, ret ? "matched" : "not matched");
if (m_trace && ret)
LogDebug("Rule Trace,\tRewritePC to %s Slot=%u Dst=%u-%u", m_name, m_toSlot, m_toIdStart, m_toIdEnd);
return ret;
}

1
RewritePC.h
View File

@@ -39,6 +39,7 @@ private:
unsigned int m_fromIdEnd;
unsigned int m_toSlot;
unsigned int m_toIdStart;
unsigned int m_toIdEnd;
bool m_trace;
CDMRLC m_lc;
CDMREmbeddedData m_embeddedLC;

10
RewriteSrc.cpp
View File

@@ -51,7 +51,10 @@ bool CRewriteSrc::processRF(CDMRData& data)
bool ret = process(data);
if (m_trace)
LogDebug("Rule Trace,\tRewriteSrc %s Slot=%u Src=%u-%u: %s", m_name, m_fromSlot, m_fromIdStart, m_fromIdEnd, ret ? "matched" : "not matched");
LogDebug("Rule Trace,\tRewriteSrc from %s Slot=%u Src=%u-%u: %s", m_name, m_fromSlot, m_fromIdStart, m_fromIdEnd, ret ? "matched" : "not matched");
if (m_trace && ret)
LogDebug("Rule Trace,\tRewriteSrc to %s Slot=%u Dst=TG%u", m_name, m_toSlot, m_toTG);
return ret;
}
@@ -61,7 +64,10 @@ bool CRewriteSrc::processNet(CDMRData& data)
bool ret = process(data);
if (m_trace)
LogDebug("Rule Trace,\tRewriteSrc %s Slot=%u Src=%u-%u: %s", m_name, m_fromSlot, m_fromIdStart, m_fromIdEnd, ret ? "matched" : "not matched");
LogDebug("Rule Trace,\tRewriteSrc from %s Slot=%u Src=%u-%u: %s", m_name, m_fromSlot, m_fromIdStart, m_fromIdEnd, ret ? "matched" : "not matched");
if (m_trace && ret)
LogDebug("Rule Trace,\tRewriteSrc to %s Slot=%u Dst=TG%u", m_name, m_toSlot, m_toTG);
return ret;
}

11
RewriteTG.cpp
View File

@@ -32,6 +32,7 @@ m_fromTGStart(fromTG),
m_fromTGEnd(fromTG + range - 1U),
m_toSlot(toSlot),
m_toTGStart(toTG),
m_toTGEnd(toTG + range - 1U),
m_trace(trace),
m_lc(FLCO_GROUP, 0U, toTG),
m_embeddedLC()
@@ -49,7 +50,10 @@ bool CRewriteTG::processRF(CDMRData& data)
bool ret = process(data);
if (m_trace)
LogDebug("Rule Trace,\tRewriteTG %s Slot=%u Dst=TG%u-TG%u: %s", m_name, m_fromSlot, m_fromTGStart, m_fromTGEnd, ret ? "matched" : "not matched");
LogDebug("Rule Trace,\tRewriteTG from %s Slot=%u Dst=TG%u-TG%u: %s", m_name, m_fromSlot, m_fromTGStart, m_fromTGEnd, ret ? "matched" : "not matched");
if (m_trace && ret)
LogDebug("Rule Trace,\tRewriteTG to %s Slot=%u Dst=TG%u-TG%u", m_name, m_toSlot, m_toTGStart, m_toTGEnd);
return ret;
}
@@ -59,7 +63,10 @@ bool CRewriteTG::processNet(CDMRData& data)
bool ret = process(data);
if (m_trace)
LogDebug("Rule Trace,\tRewriteTG %s Slot=%u Dst=TG%u-TG%u: %s", m_name, m_fromSlot, m_fromTGStart, m_fromTGEnd, ret ? "matched" : "not matched");
LogDebug("Rule Trace,\tRewriteTG from %s Slot=%u Dst=TG%u-TG%u: %s", m_name, m_fromSlot, m_fromTGStart, m_fromTGEnd, ret ? "matched" : "not matched");
if (m_trace && ret)
LogDebug("Rule Trace,\tRewriteTG to %s Slot=%u Dst=TG%u-TG%u", m_name, m_toSlot, m_toTGStart, m_toTGEnd);
return ret;
}

1
RewriteTG.h
View File

@@ -39,6 +39,7 @@ private:
unsigned int m_fromTGEnd;
unsigned int m_toSlot;
unsigned int m_toTGStart;
unsigned int m_toTGEnd;
bool m_trace;
CDMRLC m_lc;
CDMREmbeddedData m_embeddedLC;