MMDVM/DMRGateway
1
0
Fork 0
mirror of https://github.com/g4klx/DMRGateway synced 2025-12-29 10:25:41 +08:00
Code Issues Packages Projects Releases Wiki Activity

Fix pass through bug.

Browse Source
This commit is contained in:
Jonathan Naylor
2020-04-08 19:41:19 +01:00
parent 7a8548cc41
commit 55af548e6d
2 changed files with 3 additions and 3 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
DMRGateway.ini
View File

@@ -71,7 +71,7 @@ SrcRewrite=1,9990,1,9990,1
# Reflector status returns
SrcRewrite=2,4000,2,9,1001
# Dynamic rewriting of slot 2 TGs 90-999999 to TG9 to emulate reflector behaviour
TGDynRewrite=2,90,4000,5000,9,999910,9900
TGDynRewrite=2,90,4000,5000,9,999910,9990
# Pass all of the other private traffic on slot 1 and slot 2
PassAllPC=1
PassAllPC=2

4
RewriteDynTGRF.cpp
View File

@@ -107,9 +107,9 @@ PROCESS_RESULT CRewriteDynTGRF::process(CDMRData& data, bool trace)
if (std::find(m_exclTGs.cbegin(), m_exclTGs.cend(), dstId) != m_exclTGs.cend()) {
if (trace)
LogDebug("Rule Trace,\tRewriteDynTGRF from %s Slot=%u Dst=%u: matched", m_name.c_str(), m_slot, dstId);
LogDebug("Rule Trace,\tRewriteDynTGRF from %s Slot=%u Dst=%u: not matched", m_name.c_str(), m_slot, dstId);
return RESULT_IGNORED;
return RESULT_UNMATCHED;
}
if (slotNo == m_slot && dstId >= m_fromTGStart && dstId <= m_fromTGEnd) {