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Finish off the translation logic.

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This commit is contained in:
Jonathan Naylor
2020-04-01 22:56:48 +01:00
parent 10e890bdd4
commit 8fc9872aaa
5 changed files with 55 additions and 66 deletions
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10
DMRGateway.cpp
View File

@@ -1339,7 +1339,7 @@ bool CDMRGateway::createDMRNetwork1()
for (std::vector<CTGDynRewriteStruct>::const_iterator it = dynRewrites.begin(); it != dynRewrites.end(); ++it) {
LogInfo(" Dyn Rewrite: %u:TG%u-%u:TG%u <-> %u:TG%u (disc %u:TG%u)", (*it).m_slot, (*it).m_fromTG, (*it).m_slot, (*it).m_fromTG + (*it).m_range - 1U, (*it).m_slot, (*it).m_toTG, (*it).m_slot, (*it).m_discTG);
CRewriteDynTGNet* netRewriteDynTG = new CRewriteDynTGNet(m_dmr1Name, (*it).m_slot, (*it).m_fromTG, (*it).m_toTG, (*it).m_discTG, (*it).m_range);
CRewriteDynTGNet* netRewriteDynTG = new CRewriteDynTGNet(m_dmr1Name, (*it).m_slot, (*it).m_toTG);
CRewriteDynTGRF* rfRewriteDynTG = new CRewriteDynTGRF(m_dmr1Name, (*it).m_slot, (*it).m_fromTG, (*it).m_toTG, (*it).m_discTG, (*it).m_range, netRewriteDynTG);
m_dmr1RFRewrites.push_back(rfRewriteDynTG);
@@ -1488,7 +1488,7 @@ bool CDMRGateway::createDMRNetwork2()
for (std::vector<CTGDynRewriteStruct>::const_iterator it = dynRewrites.begin(); it != dynRewrites.end(); ++it) {
LogInfo(" Dyn Rewrite: %u:TG%u-%u:TG%u <-> %u:TG%u (disc %u:TG%u)", (*it).m_slot, (*it).m_fromTG, (*it).m_slot, (*it).m_fromTG + (*it).m_range - 1U, (*it).m_slot, (*it).m_toTG, (*it).m_slot, (*it).m_discTG);
CRewriteDynTGNet* netRewriteDynTG = new CRewriteDynTGNet(m_dmr2Name, (*it).m_slot, (*it).m_fromTG, (*it).m_toTG, (*it).m_discTG, (*it).m_range);
CRewriteDynTGNet* netRewriteDynTG = new CRewriteDynTGNet(m_dmr2Name, (*it).m_slot, (*it).m_toTG);
CRewriteDynTGRF* rfRewriteDynTG = new CRewriteDynTGRF(m_dmr2Name, (*it).m_slot, (*it).m_fromTG, (*it).m_toTG, (*it).m_discTG, (*it).m_range, netRewriteDynTG);
m_dmr2RFRewrites.push_back(rfRewriteDynTG);
@@ -1637,7 +1637,7 @@ bool CDMRGateway::createDMRNetwork3()
for (std::vector<CTGDynRewriteStruct>::const_iterator it = dynRewrites.begin(); it != dynRewrites.end(); ++it) {
LogInfo(" Dyn Rewrite: %u:TG%u-%u:TG%u <-> %u:TG%u (disc %u:TG%u)", (*it).m_slot, (*it).m_fromTG, (*it).m_slot, (*it).m_fromTG + (*it).m_range - 1U, (*it).m_slot, (*it).m_toTG, (*it).m_slot, (*it).m_discTG);
CRewriteDynTGNet* netRewriteDynTG = new CRewriteDynTGNet(m_dmr3Name, (*it).m_slot, (*it).m_fromTG, (*it).m_toTG, (*it).m_discTG, (*it).m_range);
CRewriteDynTGNet* netRewriteDynTG = new CRewriteDynTGNet(m_dmr3Name, (*it).m_slot, (*it).m_toTG);
CRewriteDynTGRF* rfRewriteDynTG = new CRewriteDynTGRF(m_dmr3Name, (*it).m_slot, (*it).m_fromTG, (*it).m_toTG, (*it).m_discTG, (*it).m_range, netRewriteDynTG);
m_dmr3RFRewrites.push_back(rfRewriteDynTG);
@@ -1786,7 +1786,7 @@ bool CDMRGateway::createDMRNetwork4()
for (std::vector<CTGDynRewriteStruct>::const_iterator it = dynRewrites.begin(); it != dynRewrites.end(); ++it) {
LogInfo(" Dyn Rewrite: %u:TG%u-%u:TG%u <-> %u:TG%u (disc %u:TG%u)", (*it).m_slot, (*it).m_fromTG, (*it).m_slot, (*it).m_fromTG + (*it).m_range - 1U, (*it).m_slot, (*it).m_toTG, (*it).m_slot, (*it).m_discTG);
CRewriteDynTGNet* netRewriteDynTG = new CRewriteDynTGNet(m_dmr4Name, (*it).m_slot, (*it).m_fromTG, (*it).m_toTG, (*it).m_discTG, (*it).m_range);
CRewriteDynTGNet* netRewriteDynTG = new CRewriteDynTGNet(m_dmr4Name, (*it).m_slot, (*it).m_toTG);
CRewriteDynTGRF* rfRewriteDynTG = new CRewriteDynTGRF(m_dmr4Name, (*it).m_slot, (*it).m_fromTG, (*it).m_toTG, (*it).m_discTG, (*it).m_range, netRewriteDynTG);
m_dmr4RFRewrites.push_back(rfRewriteDynTG);
@@ -1935,7 +1935,7 @@ bool CDMRGateway::createDMRNetwork5()
for (std::vector<CTGDynRewriteStruct>::const_iterator it = dynRewrites.begin(); it != dynRewrites.end(); ++it) {
LogInfo(" Dyn Rewrite: %u:TG%u-%u:TG%u <-> %u:TG%u (disc %u:TG%u)", (*it).m_slot, (*it).m_fromTG, (*it).m_slot, (*it).m_fromTG + (*it).m_range - 1U, (*it).m_slot, (*it).m_toTG, (*it).m_slot, (*it).m_discTG);
CRewriteDynTGNet* netRewriteDynTG = new CRewriteDynTGNet(m_dmr5Name, (*it).m_slot, (*it).m_fromTG, (*it).m_toTG, (*it).m_discTG, (*it).m_range);
CRewriteDynTGNet* netRewriteDynTG = new CRewriteDynTGNet(m_dmr5Name, (*it).m_slot, (*it).m_toTG);
CRewriteDynTGRF* rfRewriteDynTG = new CRewriteDynTGRF(m_dmr5Name, (*it).m_slot, (*it).m_fromTG, (*it).m_toTG, (*it).m_discTG, (*it).m_range, netRewriteDynTG);
m_dmr5RFRewrites.push_back(rfRewriteDynTG);

41
RewriteDynTGNet.cpp
View File

@@ -24,14 +24,11 @@
#include <cstdio>
#include <cassert>
CRewriteDynTGNet::CRewriteDynTGNet(const std::string& name, unsigned int slot, unsigned int fromTG, unsigned int toTG, unsigned int discTG, unsigned int range) :
CRewriteDynTGNet::CRewriteDynTGNet(const std::string& name, unsigned int slot, unsigned int toTG) :
CRewrite(),
m_name(name),
m_slot(slot),
m_fromTGStart(fromTG),
m_fromTGEnd(fromTG + range - 1U),
m_toTG(toTG),
m_discTG(discTG),
m_currentTG(0U)
{
assert(slot == 1U || slot == 2U);
@@ -47,38 +44,24 @@ bool CRewriteDynTGNet::process(CDMRData& data, bool trace)
unsigned int dstId = data.getDstId();
unsigned int slotNo = data.getSlotNo();
if (flco != FLCO_GROUP || slotNo != m_fromSlot || dstId < m_fromTGStart || dstId > m_fromTGEnd) {
if (trace) {
if (m_fromTGStart == m_fromTGEnd)
LogDebug("Rule Trace,\tRewriteDynTGNet from %s Slot=%u Dst=TG%u: not matched", m_name.c_str(), m_fromSlot, m_fromTGStart);
else
LogDebug("Rule Trace,\tRewriteDynTGNet from %s Slot=%u Dst=TG%u-TG%u: not matched", m_name.c_str(), m_fromSlot, m_fromTGStart, m_fromTGEnd);
}
if (flco != FLCO_GROUP || slotNo != m_slot || dstId != m_currentTG) {
if (trace)
LogDebug("Rule Trace,\tRewriteDynTGNet from %s Slot=%u Dst=TG%u: not matched", m_name.c_str(), m_slot, m_currentTG);
return false;
}
if (m_fromSlot != m_toSlot)
data.setSlotNo(m_toSlot);
if (m_fromTGStart != m_toTGStart) {
unsigned int newTG = dstId + m_toTGStart - m_fromTGStart;
data.setDstId(newTG);
data.setDstId(m_toTG);
processMessage(data);
}
if (trace) {
if (m_fromTGStart == m_fromTGEnd)
LogDebug("Rule Trace,\tRewriteDynTGNet from %s Slot=%u Dst=TG%u: matched", m_name.c_str(), m_fromSlot, m_fromTGStart);
else
LogDebug("Rule Trace,\tRewriteDynTGNet from %s Slot=%u Dst=TG%u-TG%u: matched", m_name.c_str(), m_fromSlot, m_fromTGStart, m_fromTGEnd);
if (m_toTGStart == m_toTGEnd)
LogDebug("Rule Trace,\tRewriteDynTGNet to %s Slot=%u Dst=TG%u", m_name.c_str(), m_toSlot, m_toTGStart);
else
LogDebug("Rule Trace,\tRewriteDynTGNet to %s Slot=%u Dst=TG%u-TG%u", m_name.c_str(), m_toSlot, m_toTGStart, m_toTGEnd);
}
if (trace)
LogDebug("Rule Trace,\tRewriteDynTGNet from %s Slot=%u Dst=TG%u: matched", m_name.c_str(), m_slot, m_currentTG);
return true;
}
void CRewriteDynTGNet::setCurrentTG(unsigned int currentTG)
{
m_currentTG = currentTG;
}

5
RewriteDynTGNet.h
View File

@@ -26,7 +26,7 @@
class CRewriteDynTGNet : public CRewrite {
public:
CRewriteDynTGNet(const std::string& name, unsigned int slot, unsigned int fromTG, unsigned int toTG, unsigned int discTG, unsigned int range);
CRewriteDynTGNet(const std::string& name, unsigned int slot, unsigned int toTG);
virtual ~CRewriteDynTGNet();
virtual bool process(CDMRData& data, bool trace);
@@ -36,10 +36,7 @@ public:
private:
std::string m_name;
unsigned int m_slot;
unsigned int m_fromTGStart;
unsigned int m_fromTGEnd;
unsigned int m_toTG;
unsigned int m_discTG;
unsigned int m_currentTG;
};

65
RewriteDynTGRF.cpp
View File

@@ -49,38 +49,47 @@ bool CRewriteDynTGRF::process(CDMRData& data, bool trace)
unsigned int dstId = data.getDstId();
unsigned int slotNo = data.getSlotNo();
if (flco != FLCO_GROUP || slotNo != m_fromSlot || dstId < m_fromTGStart || dstId > m_fromTGEnd) {
if (flco == FLCO_GROUP && slotNo == m_slot && dstId == m_toTG && m_currentTG != 0U) {
data.setDstId(m_currentTG);
processMessage(data);
if (trace)
LogDebug("Rule Trace,\tRewriteDynTGRF from %s Slot=%u Dst=TG%u: matched", m_name.c_str(), m_slot, m_toTG);
return true;
}
if (flco == FLCO_GROUP && slotNo == m_slot && dstId == m_discTG && m_currentTG != 0U) {
if (trace)
LogDebug("Rule Trace,\tRewriteDynTGRF from %s Slot=%u Dst=TG%u: matched", m_name.c_str(), m_slot, m_discTG);
m_rewriteNet->setCurrentTG(0U);
m_currentTG = 0U;
return true;
}
if (flco == FLCO_GROUP && slotNo == m_slot && dstId >= m_fromTGStart && dstId <= m_fromTGEnd) {
if (trace) {
if (m_fromTGStart == m_fromTGEnd)
LogDebug("Rule Trace,\tRewriteDynTGRF from %s Slot=%u Dst=TG%u: not matched", m_name.c_str(), m_fromSlot, m_fromTGStart);
LogDebug("Rule Trace,\tRewriteDynTGRF from %s Slot=%u Dst=TG%u: matched", m_name.c_str(), m_slot, m_fromTGStart);
else
LogDebug("Rule Trace,\tRewriteDynTGRF from %s Slot=%u Dst=TG%u-TG%u: not matched", m_name.c_str(), m_fromSlot, m_fromTGStart, m_fromTGEnd);
LogDebug("Rule Trace,\tRewriteDynTGRF from %s Slot=%u Dst=TG%u-TG%u: matched", m_name.c_str(), m_slot, m_fromTGStart, m_fromTGEnd);
}
m_rewriteNet->setCurrentTG(dstId);
m_currentTG = dstId;
return true;
}
if (trace) {
if (m_fromTGStart == m_fromTGEnd)
LogDebug("Rule Trace,\tRewriteDynTGRF from %s Slot=%u Dst=TG%u or Dst=TG%u or Dst=TG%u: not matched", m_name.c_str(), m_slot, m_fromTGStart, m_toTG, m_discTG);
else
LogDebug("Rule Trace,\tRewriteDynTGRF from %s Slot=%u Dst=TG%u-TG%u or Dst=TG%u or Dst=TG%u: not matched", m_name.c_str(), m_slot, m_fromTGStart, m_fromTGEnd, m_toTG, m_discTG);
}
return false;
}
if (m_fromSlot != m_toSlot)
data.setSlotNo(m_toSlot);
if (m_fromTGStart != m_toTGStart) {
unsigned int newTG = dstId + m_toTGStart - m_fromTGStart;
data.setDstId(newTG);
processMessage(data);
}
if (trace) {
if (m_fromTGStart == m_fromTGEnd)
LogDebug("Rule Trace,\tRewriteDynTGRF from %s Slot=%u Dst=TG%u: matched", m_name.c_str(), m_fromSlot, m_fromTGStart);
else
LogDebug("Rule Trace,\tRewriteDynTGRF from %s Slot=%u Dst=TG%u-TG%u: matched", m_name.c_str(), m_fromSlot, m_fromTGStart, m_fromTGEnd);
if (m_toTGStart == m_toTGEnd)
LogDebug("Rule Trace,\tRewriteDynTGRF to %s Slot=%u Dst=TG%u", m_name.c_str(), m_toSlot, m_toTGStart);
else
LogDebug("Rule Trace,\tRewriteDynTGRF to %s Slot=%u Dst=TG%u-TG%u", m_name.c_str(), m_toSlot, m_toTGStart, m_toTGEnd);
}
return true;
}

4
Version.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (C) 2015-2019 by Jonathan Naylor G4KLX
* Copyright (C) 2015-2020 by Jonathan Naylor G4KLX
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -19,6 +19,6 @@
#if !defined(VERSION_H)
#define VERSION_H
const char* VERSION = "20190717";
const char* VERSION = "20200401";
#endif